Motorola MC10102L, MC10102P, MC10102FN Datasheet

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Motorola MC10102L, MC10102P, MC10102FN Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Quad 2-Input NOR Gate

The MC10102 is a quad 2±input NOR gate. The MC10102 provides one gate with OR/NOR outputs.

PD = 25 mW typ/gate (No Load) tpd = 2.0 ns typ

tr, tf = 2.0 ns typ (20%±80%)

LOGIC DIAGRAM

4

2

5

6

3

7

10

14

11

12 15 13 9

VCC1 = PIN 1

VCC2 = PIN 16

VEE = PIN 8

MC10102

L SUFFIX

CERAMIC PACKAGE

CASE 620±10

P SUFFIX

PLASTIC PACKAGE

CASE 648±08

FN SUFFIX

PLCC

CASE 775±02

DIP

PIN ASSIGNMENT

VCC1

 

1

 

16

 

VCC2

 

 

 

 

 

 

 

 

 

 

 

 

AOUT

 

2

 

15

 

DOUT

 

 

 

 

 

 

 

 

 

 

 

 

BOUT

 

3

 

14

 

COUT

 

 

 

AIN

 

4

 

13

 

DIN

 

 

 

AIN

 

5

 

12

 

DIN

 

 

 

BIN

 

6

 

11

 

CIN

 

 

 

BIN

 

7

 

10

 

CIN

 

 

 

VEE

 

8

 

9

 

DOUT

 

 

 

 

 

 

 

 

 

 

 

 

Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).

3/93

Motorola, Inc. 1996

3±6

REV 5

MC10102

ELECTRICAL CHARACTERISTICS

 

 

 

 

 

 

 

Test Limits

 

 

 

 

 

 

 

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

±30°C

 

 

+25°C

 

+85°C

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Characteristic

Symbol

Test

Min

Max

Min

 

Typ

 

Max

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Supply Drain Current

IE

8

 

29

 

 

20

 

26

 

29

mAdc

Input Current

 

IinH

12

 

425

 

 

 

 

265

 

265

μAdc

 

 

IinL

12

0.5

 

0.5

 

 

 

 

0.3

 

μAdc

Output Voltage

Logic 1

VOH

9

±1.060

±0.890

±0.960

 

 

 

±0.810

±0.890

±0.700

Vdc

 

 

 

9

±1.060

±0.890

±0.960

 

 

 

±0.810

±0.890

±0.700

 

 

 

 

15

±1.060

±0.890

±0.960

 

 

 

±0.810

±0.890

±0.700

 

 

 

 

15

±1.060

±0.890

±0.960

 

 

 

±0.810

±0.890

±0.700

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Voltage

Logic 0

VOL

9

±1.890

±1.675

±1.850

 

 

 

±1.650

±1.825

±1.615

Vdc

 

 

 

9

±1.890

±1.675

±1.850

 

 

 

±1.650

±1.825

±1.615

 

 

 

 

15

±1.890

±1.675

±1.850

 

 

 

±1.650

±1.825

±1.615

 

 

 

 

15

±1.890

±1.675

±1.850

 

 

 

±1.650

±1.825

±1.615

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Threshold Voltage

Logic 1

VOHA

9

±1.080

 

±0.980

 

 

 

 

±0.910

 

Vdc

 

 

 

9

±1.080

 

±0.980

 

 

 

 

±0.910

 

 

 

 

 

15

±1.080

 

±0.980

 

 

 

 

±0.910

 

 

 

 

 

15

±1.080

 

±0.980

 

 

 

 

±0.910

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Threshold Voltage

Logic 0

VOLA

9

 

±1.655

 

 

 

 

±1.630

 

±1.595

Vdc

 

 

 

9

 

±1.655

 

 

 

 

±1.630

 

±1.595

 

 

 

 

15

 

±1.655

 

 

 

 

±1.630

 

±1.595

 

 

 

 

15

 

±1.655

 

 

 

 

±1.630

 

±1.595

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switching Times

(50Ω Load)

 

 

 

 

 

 

 

 

 

 

 

ns

Propagation Delay

t12+15±

15

1.0

3.1

1.0

 

2.0

 

2.9

1.0

3.3

 

 

 

t12±15+

15

1.0

3.1

1.0

 

2.0

 

2.9

1.0

3.3

 

 

 

t12+9+

9

1.0

3.1

1.0

 

2.0

 

2.9

1.0

3.3

 

 

 

t12±9±

9

1.0

3.1

1.0

 

2.0

 

2.9

1.0

3.3

 

Rise Time

(20 to 80%)

t15+

15

1.1

3.6

1.1

 

2.0

 

3.3

1.1

3.7

 

 

 

t9+

9

1.1

3.6

1.1

 

2.0

 

3.3

1.1

3.7

 

Fall Time

(20 to 80%)

t15±

15

1.1

3.6

1.1

 

2.0

 

3.3

1.1

3.7

 

 

 

t

9

1.1

3.6

1.1

 

2.0

 

3.3

1.1

3.7

 

MECL Data

3±7

MOTOROLA

DL122 Ð Rev 6

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