MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
TTL to Differential PECL |
MC10ELT20 |
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Translator |
MC100ELT20 |
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The MC10ELT/100ELT20 is a TTL to differential PECL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of the ELT20 makes it ideal for those applications where space, performance and low power are at a premium. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features.
The ELT20 is available in both ECL standards: the 10ELT is compatible with positive MECL 10H logic levels while the 100ELT is compatible with positive ECL 100K logic levels.
•1.5ns Typical Propagation Delay
•Differential PECL Outputs
•Small Outline SOIC Package
•PNP TTL Inputs for Minimal Loading
•Flow Through Pinouts
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
NC |
1 |
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8 |
VCC |
Q |
2 |
TTL |
7 |
D0 |
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PECL |
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Q |
3 |
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6 |
NC |
NC |
4 |
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5 |
GND |
8 
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
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PIN DESCRIPTION |
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PIN |
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FUNCTION |
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Q |
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Diff PECL Outputs |
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D |
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TTL Input |
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VCC |
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+5.0V Supply |
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GND |
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Ground |
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1/95
Motorola, Inc. 1996 |
REV 2 |
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