MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Differential PECL to TTL |
MC10ELT21 |
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Translator |
MC100ELT21 |
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The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL (Positive ECL) levels are used only +5V and ground are required. The small outline 8-lead SOIC package and the single gate of the ELT21 makes it ideal for those applications where space, performance and low power are at a premium. Because the mature MOSAIC 1.5 process is used, low cost can be added to the list of features.
The VBB output allows the ELT21 to also be used in a single-ended input mode. In this mode the VBB output is tied to the IN input for a non-inverting buffer or the IN input for an inverting buffer. If used the VBB pin should be bypassed to ground via a 0.01μF capacitor.
The ELT21 is available in both ECL standards: the 10ELT is compatible with positive MECL 10H logic levels while the 100ELT is compatible with positive ECL 100K logic levels.
•3.5ns Typical Propagation Delay
•Differential PECL Inputs
•Small Outline SOIC Package
•24mA TTL Output
•Flow Through Pinouts
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
NC |
1 |
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8 |
VCC |
D0 |
2 |
TTL |
7 |
Q0 |
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PECL |
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D0 |
3 |
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6 |
NC |
VBB |
4 |
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5 |
GND |
8 
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
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PIN DESCRIPTION |
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PIN |
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FUNCTION |
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Q |
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TTL Output |
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D |
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Diff PECL Inputs |
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VCC |
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+5.0V Supply |
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VBB |
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Reference Output |
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GND |
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Ground |
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7/96
Motorola, Inc. 1996 |
REV 3 |
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