MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Triple 2:1 Multiplexer
The MC100LVEL59 is a triple 2:1 multiplexer with differential outputs. The MC100EL59 is pin and functionally equivalent to the MC100LVEL59 but is specified for operation at the standard 100E ECL voltage supply. The output data of the muxes can be controlled individually via the select inputs or as a group via the common select input. The flexibile selection scheme makes the device useful for both data path and random logic applications.
•Individual or Common Select Controls
•20±Lead SOIC Packaging
•500ps Typical Propagation Delays
•Supports Both Standard and Low Voltage 100K ECL
•Internal Input Pulldown Resistors
•>2000V ESD Protection
Logic Diagram and Pinout: 20±Lead SOIC (Top View)
VCC |
Q0 |
Q0 |
VCC |
Q1 |
Q1 |
VCC |
Q2 |
Q2 |
VEE |
20 |
19 |
18 |
17 |
16 |
15 |
14 |
13 |
12 |
11 |
1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
COM_SEL |
D0a |
D0b |
SEL0 |
D1a |
D1b |
SEL1 |
D2a |
D2b |
SEL2 |
MC100LVEL59
MC100EL59
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D±04
TRUTH TABLE
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SEL |
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Data |
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H |
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a |
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L |
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b |
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PIN NAMES |
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Pins |
Function |
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D0a±D1a |
Input Data a |
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D0b±D1b |
Input Data b |
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SEL0±SEL1 |
Individual Select Input |
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COM_SEL |
Common Select Input |
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Q0±Q2 |
True Outputs |
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Q0±Q2 |
Inverted Outputs |
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4/95
Motorola, Inc. 1996 |
REV 1 |
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