MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Multiplexer With Latch
The MC10134 is a dual multiplexer with clocked D type latches. Each latch may be clocked separately by holding the common clock in the low state, and using the clock enable inputs for the clocking function. If the common clock is to be used to clock the latch, the clock enable (CE) inputs must be in the low state. In this mode, the enable inputs perform the function of controlling the common clock (CC).
The data select inputs determine which data input is enabled. A high (H) level on the A0 input enables data input D12 and a low (L) level on the A0 input enables data input D11. A high (H) level on the A1 input enables data input D22 and a low (L) level on the A1 input enables data input D21.
Any change on the data input will be reflected at the outputs while the clock is low. The outputs are latched on the positive transition of the clock. While the clock is in the high state, a change in the information present at the data inputs will not affect the output information.
PD = 225 mW typ/pkg (No Load) tpd = 3.0 ns typ
tr, tf = 2.5 ns typ (20%±80%)
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LOGIC DIAGRAM |
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A0 |
6 |
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A1 |
11 |
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D11 |
4 |
Q1 |
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2 |
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D12 |
5 |
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CEO |
10 |
Q1 |
CC |
3 |
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7 |
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CE1 |
15 |
Q2 |
9 |
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D21 |
13 |
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D22 |
14 |
Q2 |
12 |
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VCC1 = PIN 1 |
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VCC2 = PIN 16 |
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VEE = PIN 8 |
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TRUTH TABLE
C |
A0 |
D11 |
D12 |
Qn+1 |
L |
L |
L |
X |
L |
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L |
L |
H |
X |
H |
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L |
H |
X |
L |
L |
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L |
H |
X |
H |
H |
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H |
X |
X |
X |
Qn |
C = CE + CC
MC10134
L SUFFIX
CERAMIC PACKAGE
CASE 620±10
P SUFFIX
PLASTIC PACKAGE
CASE 648±08
FN SUFFIX
PLCC
CASE 775±02
DIP
PIN ASSIGNMENT
VCC1 |
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1 |
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16 |
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VCC2 |
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Q1 |
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2 |
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15 |
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Q2 |
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Q1 |
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3 |
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14 |
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Q2 |
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D11 |
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4 |
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13 |
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D21 |
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D12 |
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5 |
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12 |
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D22 |
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A0 |
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6 |
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11 |
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A1 |
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CC |
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7 |
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10 |
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CEO |
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VEE |
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8 |
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9 |
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CE1 |
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Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).
3/93
Motorola, Inc. 1996 |
3±17 |
REV 5 |
MC10134
ELECTRICAL CHARACTERISTICS
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Test Limits |
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Pin |
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±30°C |
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+25°C |
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+85°C |
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Under |
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Characteristic |
Symbol |
Test |
Min |
Max |
Min |
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Typ |
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Max |
Min |
Max |
Unit |
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Power Supply Drain Current |
IE |
8 |
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60 |
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55 |
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60 |
mAdc |
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Input Current |
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IinH |
4 |
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460 |
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290 |
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290 |
μAdc |
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5 |
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460 |
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290 |
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290 |
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6 |
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425 |
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265 |
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265 |
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7 |
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460 |
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290 |
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290 |
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10 |
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425 |
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265 |
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265 |
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IinL |
4* |
0.5 |
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0.5 |
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0.3 |
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μAdc |
Output Voltage |
Logic 1 |
VOH |
2 |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
Vdc |
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2 |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
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Output Voltage |
Logic 0 |
VOL |
2 |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
Vdc |
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2 |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
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Threshold Voltage |
Logic 1 |
VOHA |
2 |
±1.080 |
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±0.980 |
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±0.910 |
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Vdc |
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2 |
±1.080 |
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±0.980 |
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±0.910 |
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Threshold Voltage |
Logic 0 |
VOLA |
2 |
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±1.655 |
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±1.630 |
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±1.595 |
Vdc |
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2 |
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±1.655 |
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±1.630 |
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±1.595 |
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Switching Times |
(50Ω Load) |
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ns |
Propagation Delay |
Data |
t4+2+ |
2 |
1.0 |
3.5 |
1.0 |
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3.3 |
1.0 |
3.6 |
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Clock |
t10±2+ |
2 |
1.0 |
6.0 |
1.0 |
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5.7 |
1.0 |
6.3 |
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Select |
t6+2+ |
2 |
1.0 |
4.8 |
1.0 |
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4.6 |
1.0 |
5.0 |
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Setup Time |
Data |
tsetup |
2 |
2.5 |
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2.5 |
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2.5 |
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Select |
tsetup |
2 |
3.5 |
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3.5 |
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3.5 |
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Hold Time |
Data |
thold |
2 |
1.5 |
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1.5 |
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1.5 |
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Select |
thold |
2 |
1.0 |
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1.0 |
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1.0 |
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Rise Time |
(20 to 80%) |
t2+ |
2 |
1.5 |
3.7 |
1.5 |
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3.5 |
1.5 |
3.8 |
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Fall Time |
(20 to 80%) |
t2± |
2 |
1.5 |
3.7 |
1.5 |
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3.5 |
1.5 |
3.8 |
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* All other inputs tested in the same manner.
MOTOROLA |
3±18 |
MECL Data |
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DL122 Ð Rev 6 |
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