MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad Bus Driver
The MC10192 contains four line drivers with complementary outputs. Each
driver has a Data (D) input and shares an Enable (E) input with another driver. The two driver outputs are the uncommitted collectors of a pair of NPN transistors operating as a current switch. Each driver accepts 10K MECL input signals and provides a nominal signal swing of 800 mV across a 50 Ω load at each output collector. Outputs can drive higher values of load resistance, provided that the combination of IR drop and load return voltage VLR does not cause an output collector to go more negative than ±2.4 V with respect to VCC. To avoid output transistor breakdown, the load return voltage should not be more positive than +5.5 V with respect to VCC. When the E input is high, both output transistors of a driver are nonconducting. When not used, the E inputs, as well as the D inputs, may be left open.
Open Collector Outputs Drive Terminated Lines or Transformers
50 kΩ Input Pulldown Resistors on All Inputs (Unused Inputs May Be Left Open)
Power Dissipation = 575 mW typ/pkg (No Load) Propagation Delay= 3.5 ns typ (E Ð Output)
3.0 ns typ (D Ð Output)
LOGIC DIAGRAM
E1 |
7 |
3 |
Z1 |
D1 |
5 |
4 |
Z1 |
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1 |
Z2 |
D2 |
6 |
2 |
Z2 |
D3 |
10 |
15 |
Z3 |
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14 |
Z3 |
D4 |
11 |
13 |
Z4 |
E2 |
9 |
12 |
Z4 |
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VCC = PIN 16 |
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VEE = PIN 8 |
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TRUTH TABLE |
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Inputs |
Output |
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E |
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D |
Z |
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Z |
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H |
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X |
H |
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H |
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L |
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H |
H |
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L |
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L |
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L |
L |
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H |
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Note: Unused outputs must be terminated to VCC for proper operation.
MC10192
L SUFFIX
CERAMIC PACKAGE
CASE 620±10
P SUFFIX
PLASTIC PACKAGE
CASE 648±08
FN SUFFIX
PLCC
CASE 775±02
DIP
PIN ASSIGNMENT
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Z2 |
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1 |
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16 |
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VCC |
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Z3 |
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Z2 |
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2 |
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15 |
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Z1 |
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3 |
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14 |
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Z3 |
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Z4 |
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Z1 |
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4 |
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13 |
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D1 |
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5 |
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12 |
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Z4 |
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D2 |
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6 |
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11 |
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D4 |
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D3 |
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E1 |
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7 |
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10 |
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VEE |
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8 |
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9 |
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E2 |
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Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).
3/93
Motorola, Inc. 1996 |
3±160 |
REV 5 |
MC10192
ELECTRICAL CHARACTERISTICS
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Test Limits |
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Pin |
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±30°C |
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+25°C |
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+85°C |
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Under |
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Characteristic |
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Symbol |
Test |
Min |
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Max |
Min |
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Max |
Min |
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Max |
Unit |
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Power Supply Drain Current |
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IE |
8 |
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154 |
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140 |
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154 |
mAdc |
Input Current |
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IinH |
5 |
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350 |
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220 |
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220 |
μAdc |
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IinL |
5 |
0.5 |
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0.5 |
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0.3 |
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μAdc |
Output Current High |
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Logic 1 |
IOH |
2 |
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2.0 |
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mAdc |
Output Current Low |
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Logic 0 |
IOL |
2 |
13.5 |
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18.0 |
14.0 |
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18.0 |
14.0 |
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19.0 |
mAdc |
Threshold Current High |
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Logic 1 |
IOHC |
2 |
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2.0 |
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2.0 |
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2.0 |
mAdc |
Threshold Current Low |
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Logic 0 |
IOLC |
2 |
13.5 |
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14.0 |
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14.0 |
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mAdc |
Output Sink Current Low |
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Logic 0 |
IOS |
2 |
13.3 |
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13.9 |
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13.3 |
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mAdc |
Load Return Voltage Absolute Max |
VLR |
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5.5 |
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5.5 |
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5.5 |
V |
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Rating (Note 1.) |
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Output Voltage Low (Note 2.) |
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VOLS |
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±2.4 |
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V |
Switching Times |
(50Ω Load) |
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ns |
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Propagation Delay |
E to Output |
tPHL |
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2.0 |
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6.0 |
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D to Output |
tPLH |
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1.5 |
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4.5 |
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Rise/Fall Time |
(20 to 80%) |
tTLH |
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3.3 |
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tTHL |
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1.The 5.5V value is a maximum rating, do not exceed. A 270Ω resistor will prevent output transistor breakdown.
2.Limitations of load resistor and load return voltage combinations. Refer to page 3±160 description.
ELECTRICAL CHARACTERISTICS (continued)
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TEST VOLTAGE VALUES (Volts) |
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@ Test Temperature |
VIHmax |
VILmin |
VIHAmin |
VILAmax |
VEE |
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±30°C |
±0.890 |
±1.890 |
±1.205 |
±1.500 |
±5.2 |
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+25°C |
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±0.810 |
±1.850 |
±1.105 |
±1.475 |
±5.2 |
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+85°C |
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±0.700 |
±1.825 |
±1.035 |
±1.440 |
±5.2 |
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Pin |
TEST VOLTAGE APPLIED TO PINS LISTED BELOW |
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Under |
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(VCC) |
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Characteristic |
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Symbol |
Test |
VIHmax |
VILmin |
VIHAmin |
VILAmax |
VEE |
Gnd |
Power Supply Drain Current |
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IE |
8 |
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8 |
16 |
Input Current |
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IinH |
5 |
5 |
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8 |
16 |
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IinL |
5 |
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5 |
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8 |
16 |
Output Current High |
Logic 1 |
IOH |
2 |
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5,6,10,11 |
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8 |
16 |
Output Current Low |
Logic 0 |
IOL |
2 |
5,6,10,11 |
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8 |
16 |
Threshold Current High |
Logic 1 |
IOHC |
2 |
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5,7,9,10,11 |
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6 |
8 |
16 |
Threshold Current Low |
Logic 0 |
IOLC |
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5,10,11 |
7,9 |
6 |
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8 |
16 |
Output Sink Current Low |
Logic 0 |
IOS |
2 |
5,6,10,11 |
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8 |
16 |
Load Return Voltage Absolute Max |
VLR |
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8 |
16 |
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Rating (Note 1.) |
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Output Voltage Low (Note 2.) |
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VOLS |
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8 |
16 |
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50±ohm resistor to ±2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.
MECL Data |
3±161 |
MOTOROLA |
DL122 Ð Rev 6 |
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