Motorola MC10106L, MC10106P, MC10106FN Datasheet

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Motorola MC10106L, MC10106P, MC10106FN Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Triple 4-3-3-Input NOR Gate

The MC10106 is a triple 4±3±3 input NOR gate.

PD = 30 mW typ/gate (No Load) tpd = 2.0 ns typ

tr, tf = 2.0 ns typ (20%±80%)

LOGIC DIAGRAM

4

5

3 6

7

9

 

10

2

11

 

12

 

13

15

14

 

VCC1

= PIN 1

VCC2

= PIN 16

VEE

= PIN 8

MC10106

L SUFFIX

CERAMIC PACKAGE

CASE 620±10

P SUFFIX

PLASTIC PACKAGE

CASE 648±08

FN SUFFIX

PLCC

CASE 775±02

DIP

PIN ASSIGNMENT

VCC1

 

1

 

16

 

VCC2

 

 

 

 

 

 

 

 

 

 

 

 

BOUT

 

2

 

15

 

COUT

 

 

 

 

 

 

 

 

 

 

CIN

AOUT

 

3

 

14

 

 

 

 

AIN

 

4

 

13

 

CIN

 

 

 

AIN

 

5

 

12

 

CIN

 

 

 

AIN

 

6

 

11

 

BIN

 

 

 

AIN

 

7

 

10

 

BIN

 

 

 

VEE

 

8

 

9

 

BIN

 

 

 

 

 

 

 

 

 

 

 

 

Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).

3/93

Motorola, Inc. 1996

3±26

REV 5

MC10106

ELECTRICAL CHARACTERISTICS

 

 

 

 

 

 

 

Test Limits

 

 

 

 

 

 

 

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

±30°C

 

 

+25°C

 

+85°C

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Characteristic

Symbol

Test

Min

Max

Min

 

Typ

 

Max

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Supply Drain Current

IE

8

 

23

 

 

17

 

21

 

23

mAdc

Input Current

 

IinH

4

 

425

 

 

 

 

265

 

265

μAdc

 

 

IinL

4

0.5

 

0.5

 

 

 

 

0.3

 

μAdc

Output Voltage

Logic 1

VOH

3

±1.060

±0.890

±0.960

 

 

 

±0.810

±0.890

±0.700

Vdc

 

 

 

2

±1.060

±0.890

±0.960

 

 

 

±0.810

±0.890

±0.700

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Output Voltage

Logic 0

VOL

3

±1.890

±1.675

±1.850

 

 

 

±1.650

±1.825

±1.615

Vdc

 

 

 

2

±1.890

±1.675

±1.850

 

 

 

±1.650

±1.825

±1.615

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Threshold Voltage

Logic 1

VOHA

3

±1.080

 

±0.980

 

 

 

 

±0.910

 

Vdc

 

 

 

2

±1.080

 

±0.980

 

 

 

 

±0.910

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Threshold Voltage

Logic 0

VOLA

3

 

±1.655

 

 

 

 

±1.630

 

±1.595

Vdc

 

 

 

2

 

±1.655

 

 

 

 

±1.630

 

±1.595

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Switching Times

(50Ω Load)

 

 

 

 

 

 

 

 

 

 

 

ns

Propagation Delay

t4+3±

3

1.0

3.1

1.0

 

2.0

 

2.9

1.0

3.3

 

 

 

t4±3+

3

1.0

3.1

1.0

 

2.0

 

2.9

1.0

3.3

 

Rise Time

(20 to 80%)

t3+

3

1.1

3.6

1.1

 

2.0

 

3.3

1.1

3.7

 

Fall Time

(20 to 80%)

t

3

1.1

3.6

1.1

 

2.0

 

3.3

1.1

3.7

 

ELECTRICAL CHARACTERISTICS (continued)

 

 

 

 

 

TEST VOLTAGE VALUES (Volts)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

@ Test Temperature

VIHmax

VILmin

VIHAmin

VILAmax

VEE

 

 

 

 

±30°C

±0.890

±1.890

±1.205

±1.500

±5.2

 

 

 

 

+25°C

 

 

 

 

 

 

 

 

 

±0.810

±1.850

±1.105

±1.475

±5.2

 

 

 

 

+85°C

 

 

 

 

 

 

 

 

 

±0.700

±1.825

±1.035

±1.440

±5.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

TEST VOLTAGE APPLIED TO PINS LISTED BELOW

 

 

 

 

Under

 

 

 

 

 

(VCC)

 

 

 

 

 

 

 

 

Characteristic

 

Symbol

Test

VIHmax

VILmin

VIHAmin

VILAmax

VEE

Gnd

Power Supply Drain Current

IE

8

 

 

 

 

8

1, 16

Input Current

 

IinH

4

4

 

 

 

8

1, 16

 

 

IinL

4

 

4

 

 

8

1, 16

Output Voltage

Logic 1

VOH

3

 

 

 

 

8

1, 16

 

 

 

2

 

 

 

 

8

1, 16

 

 

 

 

 

 

 

 

 

 

Output Voltage

Logic 0

VOL

3

4

 

 

 

8

1, 16

 

 

 

2

9

 

 

 

8

1, 16

 

 

 

 

 

 

 

 

 

 

Threshold Voltage

Logic 1

VOHA

3

 

 

 

4

8

1, 16

 

 

 

2

 

 

 

9

8

1, 16

 

 

 

 

 

 

 

 

 

 

Threshold Voltage

Logic 0

VOLA

3

 

 

4

 

8

1, 16

 

 

 

2

 

 

9

 

8

1, 16

 

 

 

 

 

 

 

 

 

 

Switching Times

(50Ω Load)

 

 

 

 

Pulse In

Pulse Out

±3.2 V

+2.0 V

 

 

 

 

 

 

 

 

 

 

Propagation Delay

 

t4+3±

3

 

 

4

3

8

1, 16

 

 

t4±3+

3

 

 

4

3

8

1, 16

Rise Time

(20 to 80%)

t3+

3

 

 

4

3

8

1, 16

Fall Time

(20 to 80%)

t

3

 

 

4

3

8

1, 16

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50-ohm resistor to ±2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.

MECL Data

3±27

MOTOROLA

DL122 Ð Rev 6

 

 

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