MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Bi-Quinary Counter
The MC10138 is a four bit counter capable of divide by two, five, or ten functions. It is composed of four set±reset master±slave flip±flops. Clock inputs trigger on the positive going edge of the clock pulse.
Set or reset input override the clock, allowing asynchronous ªsetº or ªclear.º Individual set and common reset inputs are provided, as well as complementary outputs for the first and fourth bits.
PD = 370 mW typ/pkg (No Load)
ftog = 150 MHz typ
tr, tf = 2.5 ns typ (20%±80%)
LOGIC DIAGRAM
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S0 |
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Q0 |
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S1 |
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Q1 |
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S2 |
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Q2 |
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S3 |
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Q3 |
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11 |
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15 |
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10 |
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13 |
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D1 |
Q |
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D1 |
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Q |
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D1 |
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Q |
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D1 |
Q' |
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12 |
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Q' |
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D2 |
Q' |
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C1 |
Q' |
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D2 |
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Q |
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Clock |
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C1 |
Q |
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C2 |
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Q |
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C2 |
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Q |
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C2 |
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Q |
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R |
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R |
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R |
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R |
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9 |
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Reset |
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14 |
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Q0 |
C2 |
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Q3 |
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VCC1 = PIN 1; VCC2 = PIN 16; VEE = PIN 8
COUNTER TRUTH TABLES
BI±QUINARY
(Clock connected to C2 and Q3 connected to C1)
COUNT |
Q1 |
Q2 |
Q3 |
Q0 |
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0 |
L |
L |
L |
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1 |
H |
L |
L |
L |
2 |
L |
H |
L |
L |
3 |
H |
H |
L |
L |
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4 |
L |
L |
H |
L |
5 |
L |
L |
L |
H |
6 |
H |
L |
L |
H |
7 |
L |
H |
L |
H |
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8 |
H |
H |
L |
H |
9 |
L |
L |
H |
H |
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BCD
(Clock connected to C1 and Q0 connected to C2)
COUNT |
Q0 |
Q1 |
Q2 |
Q3 |
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0 |
L |
L |
L |
L |
1 |
H |
L |
L |
L |
2 |
L |
H |
L |
L |
3 |
H |
H |
L |
L |
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4 |
L |
L |
H |
L |
5 |
H |
L |
H |
L |
6 |
L |
H |
H |
L |
7 |
H |
H |
H |
L |
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8 |
L |
L |
L |
H |
9 |
H |
L |
L |
H |
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COUNTER STATE DIAGRAM Ð POSITIVE LOGIC
MC10138
L SUFFIX
CERAMIC PACKAGE
CASE 620±10
P SUFFIX
PLASTIC PACKAGE
CASE 648±08
FN SUFFIX
PLCC
CASE 775±02
DIP
PIN ASSIGNMENT
VCC1 |
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1 |
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16 |
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VCC2 |
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Q3 |
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2 |
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15 |
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Q0 |
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Q3 |
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3 |
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14 |
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Q0 |
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Q2 |
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4 |
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13 |
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Q1 |
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S3 |
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5 |
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12 |
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C1 |
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S2 |
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6 |
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11 |
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S0 |
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C2 |
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7 |
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10 |
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S1 |
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VEE |
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8 |
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9 |
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RESET |
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Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).
CLOCK CONNECTED TO C2 |
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Q0 CONNECTED TO C2 |
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0 |
0 |
1 |
2 |
3 |
4 |
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4 |
7 |
1 |
14 |
10 |
11 |
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5 |
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15 |
12 |
13 |
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6 |
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3 |
2 |
9 |
8 |
7 |
6 |
5 |
3/93 |
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Motorola, Inc. 1996 |
3±41 |
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REV 5 |
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MC10138
ELECTRICAL CHARACTERISTICS
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Test Limits |
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Pin |
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±30°C |
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+25°C |
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+85°C |
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Under |
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Characteristic |
Symbol |
Test |
Min |
Max |
Min |
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Typ |
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Max |
Min |
Max |
Unit |
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Power Supply Drain Current |
IE |
8 |
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97 |
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70 |
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88 |
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97 |
mAdc |
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Input Current |
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IinH |
12 |
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350 |
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220 |
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220 |
μAdc |
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5,6,10,11 |
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390 |
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245 |
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245 |
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7 |
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460 |
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290 |
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290 |
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9 |
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650 |
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410 |
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IinL |
All |
0.5 |
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0.5 |
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0.3 |
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μAdc |
Output Voltage |
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Logic 1 |
VOH |
3,14 (3.) |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
Vdc |
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2,4,13,15 (2.) |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
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Output Voltage |
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Logic 0 |
VOL |
3,14 (2.) |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
Vdc |
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2,4,13,15 (3.) |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
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Threshold Voltage |
Logic 1 |
VOHA |
2,4,13,15 (2.) |
±1.080 |
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±0.980 |
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±0.910 |
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Vdc |
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3,14 (3.) |
±1.080 |
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±0.980 |
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±0.910 |
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13,15 (2.) |
±1.080 |
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±0.980 |
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±0.910 |
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Threshold Voltage |
Logic 0 |
VOLA |
2,4,13,15 (3.) |
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±1.655 |
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±1.630 |
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±1.595 |
Vdc |
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3,14 (2.) |
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±1.655 |
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±1.630 |
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±1.595 |
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13,15 (3.) |
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±1.655 |
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±1.630 |
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±1.595 |
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Switching Times |
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(50Ω Load) |
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ns |
Propagation |
Clock Delays |
t12+15+ |
15 |
1.4 |
5.0 |
1.5 |
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3.5 |
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4.8 |
1.5 |
5.3 |
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Delay |
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t12+14+ |
14 |
1.4 |
5.0 |
1.5 |
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3.5 |
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4.8 |
1.5 |
5.3 |
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t7+13+ |
13 |
1.4 |
5.2 |
1.5 |
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3.5 |
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5.0 |
1.5 |
5.5 |
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t7+4+ |
4 |
1.4 |
5.2 |
1.5 |
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3.5 |
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5.0 |
1.5 |
5.5 |
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t7+2+ |
2 |
1.4 |
5.2 |
1.5 |
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3.5 |
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5.0 |
1.5 |
5.5 |
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t7+3+ |
3 |
1.4 |
5.2 |
1.5 |
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3.5 |
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5.0 |
1.5 |
5.5 |
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t12+15± |
15 |
1.4 |
5.0 |
1.5 |
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3.5 |
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4.8 |
1.5 |
5.3 |
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t12+14± |
14 |
1.4 |
5.0 |
1.5 |
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3.5 |
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4.8 |
1.5 |
5.3 |
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t7+13± |
13 |
1.4 |
5.2 |
1.5 |
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3.5 |
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5.0 |
1.5 |
5.5 |
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t7+4± |
4 |
1.4 |
5.2 |
1.5 |
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3.5 |
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5.0 |
1.5 |
5.5 |
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t7+2± |
2 |
1.4 |
5.2 |
1.5 |
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3.5 |
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5.0 |
1.5 |
5.5 |
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t7+3± |
3 |
1.4 |
5.2 |
1.5 |
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3.5 |
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5.0 |
1.5 |
5.5 |
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Set Delay |
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t11+15+ |
15 |
1.4 |
5.2 |
1.5 |
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5.0 |
1.5 |
5.5 |
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t11+14± |
14 |
1.4 |
5.2 |
1.5 |
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5.0 |
1.5 |
5.5 |
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Reset Delay |
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t9+14+ |
14 |
1.4 |
5.2 |
1.5 |
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5.0 |
1.5 |
5.5 |
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t9+15± |
15 |
1.4 |
5.2 |
1.5 |
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5.0 |
1.5 |
5.5 |
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Rise Time |
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(20 to 80%) |
t14+ |
14 |
1.1 |
4.7 |
1.1 |
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2.5 |
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4.5 |
1.1 |
5.0 |
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t15+ |
15 |
1.1 |
4.7 |
1.1 |
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2.5 |
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4.5 |
1.1 |
5.0 |
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Fall Time |
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(20 to 80%) |
t14± |
14 |
1.1 |
4.7 |
1.1 |
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2.5 |
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4.5 |
1.1 |
5.0 |
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t15± |
15 |
1.1 |
4.7 |
1.1 |
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2.5 |
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4.5 |
1.1 |
5.0 |
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Counting Frequency |
fcount |
2 |
125 |
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125 |
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150 |
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125 |
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MHz |
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15 |
125 |
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125 |
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150 |
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125 |
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1. Individually test each input; apply VILmin to pin under test. VIHmax
VILmin
VIHmax
VILmin
to pins 5, 6, 10, and 11 prior to applying test voltage indicated.
to pin 9 prior to applying test voltage indicated.
3±42 |
MECL Data |
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DL122 Ð Rev 6 |
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