Motorola MC10158P, MC10158FN, MC10158L Datasheet

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Motorola MC10158P, MC10158FN, MC10158L Datasheet

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Quad 2-Input Multiplexer

(Non-Inverting)

The MC10158 is a quad two channel multiplexer. A common select input determines which data inputs are enabled. A high (H) level enables data inputs D00, D10, D20, and D30 and a low (L) level enables data inputs D01, D11, D21, and D31.

PD = 197 mW typ/pkg (No Load) tpd = 2.5 ns typ (Data to Q)

3.2 ns typ (Select to Q) tr, tf = 2.5 ns typ (20%±80%)

LOGIC DIAGRAM

SE-

LECT 9

D01

5

D00

6

D11

3

D10

4

D21

12

D20

13

D31

10

D30 11

TRUTH TABLE

Select

D0

D1

Q

L

X

L

L

L

X

H

H

H

L

X

L

H

H

X

H

 

 

 

 

1 Q0

2 Q1

15 Q2

14 Q3

VCC = PIN 16

VEE = PIN 8

MC10158

L SUFFIX

CERAMIC PACKAGE

CASE 620±10

P SUFFIX

PLASTIC PACKAGE

CASE 648±08

FN SUFFIX

PLCC

CASE 775±02

DIP

PIN ASSIGNMENT

Q0

 

1

 

16

 

VCC

 

 

 

Q1

 

2

 

15

 

Q2

 

 

 

D11

 

3

 

14

 

Q3

 

 

 

D10

 

4

 

13

 

D20

 

 

 

D01

 

5

 

12

 

D21

 

 

 

D00

 

6

 

11

 

D30

 

 

 

N C

 

7

 

10

 

D31

 

 

 

VEE

 

8

 

9

 

SELECT

 

 

 

 

 

 

 

 

 

 

Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±36 of the Motorola MECL Data Book (DL122/D).

3/93

Motorola, Inc. 1996

3±61

REV 5

MC10158

ELECTRICAL CHARACTERISTICS

 

 

 

 

 

 

 

Test Limits

 

 

 

 

 

 

 

Pin

 

 

 

 

 

 

 

 

 

 

 

 

 

±30°C

 

 

+25°C

 

+85°C

 

 

 

 

Under

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Characteristic

Symbol

Test

Min

Max

Min

 

Typ

 

Max

Min

Max

Unit

 

 

 

 

 

 

 

 

 

 

 

 

 

Power Supply Drain Current

IE

8

 

53

 

 

38

 

48

 

53

mAdc

Input Current

 

IinH

9

 

360

 

 

 

 

225

 

225

μAdc

 

 

 

5

 

400

 

 

 

 

250

 

250

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IinL

5

0.5

 

0.5

 

 

 

 

0.3

 

μAdc

Output Voltage

Logic 1

VOH

1

±1.060

±0.890

±0.960

 

 

 

±0.810

±0.890

±0.700

Vdc

Output Voltage

Logic 0

VOL

1

±1.890

±1.675

±1.850

 

 

 

±1.650

±1.825

±1.615

Vdc

Threshold Voltage

Logic 1

VOHA

1

±1.080

 

±0.980

 

 

 

 

±0.910

 

Vdc

Threshold Voltage

Logic 0

VOLA

1

 

±1.655

 

 

 

 

±1.630

 

±1.595

Vdc

Switching Times

(50Ω Load)

 

 

 

 

 

 

 

 

 

 

 

ns

Propagation

Data Input

t5±1±

1

1.3

3.1

1.2

 

2.5

 

3.0

1.3

3.2

 

Delay

Select Input

t9+1+

1

2.5

4.8

2.4

 

3.2

 

4.5

2.5

4.8

 

Rise Time

(20 to 80%)

t1+

1

1.6

3.4

1.5

 

2.5

 

3.3

1.6

3.4

 

Fall Time

(20 to 80%)

t

1

1.6

3.4

1.5

 

2.5

 

3.3

1.6

3.4

 

ELECTRICAL CHARACTERISTICS (continued)

 

 

 

 

 

TEST VOLTAGE VALUES (Volts)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

@ Test Temperature

VIHmax

VILmin

VIHAmin

VILAmax

VEE

 

 

 

 

±30°C

±0.890

±1.890

±1.205

±1.500

±5.2

 

 

 

 

+25°C

 

 

 

 

 

 

 

 

 

±0.810

±1.850

±1.105

±1.475

±5.2

 

 

 

 

+85°C

 

 

 

 

 

 

 

 

 

±0.700

±1.825

±1.035

±1.440

±5.2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pin

TEST VOLTAGE APPLIED TO PINS LISTED BELOW

 

 

 

 

Under

 

 

 

 

 

(VCC)

 

 

 

 

 

 

 

 

Characteristic

 

Symbol

Test

VIHmax

VILmin

VIHAmin

VILAmax

VEE

Gnd

Power Supply Drain Current

IE

8

 

 

 

 

8

16

Input Current

 

IinH

9

9

 

 

 

8

16

 

 

 

5

5

 

 

 

8

16

 

 

 

 

 

 

 

 

 

 

 

 

IinL

5

 

5

 

 

8

16

Output Voltage

Logic 1

VOH

1

5

 

 

 

8

16

Output Voltage

Logic 0

VOL

1

 

 

 

 

8

16

Threshold Voltage

Logic 1

VOHA

1

 

 

5

 

8

16

Threshold Voltage

Logic 0

VOLA

1

 

 

 

5

8

16

Switching Times

(50Ω Load)

 

 

+1.11V

+0.31V

Pulse In

Pulse Out

±3.2 V

+2.0 V

 

 

 

 

 

 

 

 

 

 

Propagation Delay

Data Input

t5±1±

1

 

 

5

1

8

16

 

Select Input

t9+1+

1

6

 

9

1

8

16

Rise Time

(20 to 80%)

t1+

1

 

 

5

1

8

16

Fall Time

(20 to 80%)

t

1

 

 

5

1

8

16

Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50±ohm resistor to ±2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner.

MOTOROLA

3±62

MECL Data

 

 

DL122 Ð Rev 6

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