MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
2, 4, 8 Clock
Generation Chip
The MC10/100EL34 is a low skew 2, 4, 8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPS Data Book DL140/D). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01μF capacitor. The VBB output is designed to act as the switching reference for the input of the EL34 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current.
The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.
Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system.
•50ps Output-to-Output Skew
•Synchronous Enable/Disable
•Master Reset for Synchronization
•75kΩ Internal Input Pulldown Resistors
•>1000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VCC |
EN |
NC |
CLK |
CLK |
VBB |
MR |
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VEE |
16 |
15 |
14 |
13 |
12 |
11 |
10 |
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9 |
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D |
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Q |
R |
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2 |
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4 |
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8 |
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Q |
R |
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Q |
R |
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Q |
R |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
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8 |
Q0 |
Q0 |
VCC |
Q1 |
Q1 |
VCC |
Q2 |
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Q2 |
MC10EL34
MC100EL34
16
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B-05
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PIN DESCRIPTION |
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PIN |
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FUNCTION |
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CLK |
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Diff Clock Inputs |
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EN |
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Sync Enable |
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MR |
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Master Reset |
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VBB |
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Reference Output |
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Q0 |
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Diff 2 Outputs |
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Q1 |
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Diff 4 Outputs |
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Q2 |
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Diff 8 Outputs |
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FUNCTION TABLE
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FUNCTION |
CLK |
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EN |
MR |
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Z |
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L |
L |
Divide |
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ZZ |
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H |
L |
Hold Q0±3 |
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X |
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X |
H |
Reset Q0±3 |
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Z = Low-to-High Transition
ZZ = High-to-Low Transition
12/93
Motorola, Inc. 1996 |
REV 2 |
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