MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4 Divider
The MC100LVEL33 is an integrated 4 divider. The differential clock inputs and the VBB allow a differential, single-ended or AC coupled interface to the device. If used, the VBB output should be bypassed to ground with a 0.01μF capacitor. Also note that the VBB is designed to be used as an input bias on the EL33 only, the VBB output has limited current sink and source capability. The LVEL is functionally equivalent to the EL33 and works from a low voltage supply.
The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple LVEL33's in a system.
•630ps Propagation Delay
•4.0GHz Toggle Frequency
•High Bandwidth Output Transitions
•Operates from ±3.3V (or 3.3V) Supply
•75kΩ Internal Input Pulldown Resistors
•>2000V ESD Protection
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
Reset |
1 |
8 |
VCC |
||||||
|
|
|
|
R |
|
|
|||
CLK |
2 |
|
|
7 |
Q |
||||
|
|||||||||
|
|
|
|
4 |
|
|
|||
|
|
|
3 |
|
|
|
6 |
|
|
CLK |
|
|
|
Q |
|||||
|
|||||||||
VBB |
4 |
5 |
VEE |
||||||
MC100LVEL33
8 
1
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
|
|
PIN DESCRIPTION |
||
|
|
|
|
|
|
PIN |
|
FUNCTION |
|
|
|
|
|
|
|
CLK |
|
Clock Inputs |
|
|
Reset |
|
Asynch Reset |
|
|
VBB |
|
Ref Voltage Output |
|
|
Q |
|
Data Ouputs |
|
|
|
|
|
|
|
|
|
|
|
8/96
Motorola, Inc. 1996 |
REV 0 |
Loading...