MC10E104FNR2
FFV
CCO
NCD
4a
D
4b
D
3a
LOGIC DIAGRAM
D
3b
D
2a
D
2b
V
EE
D
1a
D
1b
D
0a
26
27
28
2
3
4
25 24 23 22 21 20 19
18
17
16
15
14
13
12
115 6 7 8 9 10
Q
4
Q
4
V
CC
Q
3
Q
3
Q
2
Q
2
D
0b
V
CCO
Q
0
Q
0
Q
1
Q
1
V
CCO
D
0a
D
0b
D
1a
D
1b
D
2a
D
2b
D
3a
D
3b
D
4a
D
4b
F
F
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
Q
4
Q
4
1
* All V
CC
and V
CCO
pins are tied together on the die.
Pinout: 28-Lead PLCC (Top View)
SEMICONDUCTOR TECHNICAL DATA
2–1
REV 2
Motorola, Inc. 1996
12/93
The MC10E/100E104 is a quint 2-input AND/NAND gate. The function
output F is the OR of all five AND gate outputs, while F
is the NOR. The Q
outputs need not be terminated if only the F outputs are to be used.
• 600ps Max. Propagation Delay
• OR/NOR Function Outputs
• Extended 100E V
EE
Range of – 4.2V to – 5.46V
• 75kΩ Input Pulldown Resistors
PIN NAMES
Pin Function
D
0a
– D
4b
Data Inputs
Q
0
– Q
4
AND Outputs
Q
0
– Q
4
NAND Outputs
F OR Output
F NOR Output
FUNCTION OUTPUTS
F = (D
0a
• D
0b
) + (D
1a
• D
1b
) + (D
2a
• D
2b
) +
(D
3a
• D
3b
) + (D
4a
• D
4b
)
QUINT 2-INPUT
AND/NAND GATE
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
MC10E104 MC100E104
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 4
2–2
DC CHARACTERISTICS (V
EE
= V
EE
(min) to V
EE
(max); V
CC
= V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
I
IH
Input HIGH Current 200 200 200 µA
I
EE
Power Supply Current mA
10E 38 46 38 46 38 46
100E 38 46 38 46 44 53
AC CHARACTERISTICS (V
EE
= V
EE
(min) to V
EE
(max); V
CC
= V
CCO
= GND)
0°C 25°C 85°C
Symbol Characteristic min typ max min typ max min typ max Unit Condition
t
PLH
Propagation Delay to Output ps
t
PHL
D to Q 225 385 600 225 385 600 225 385 600
D to F 500 725 1000 500 725 1000 500 725 1000
t
SKEW
Within-Device Skew ps
D to Q 75 75 75 1
t
r
Rise/Fall Times ps
t
f
20 - 80%
Q 275 425 700 275 425 700 275 425 700
F 300 475 700 300 475 700 300 475 700
1. Within-device skew is defined as identical transitions on similar paths through a device.
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