MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3 Bit Differential Flip Flop
The MC10E/100E431 is a 3-bit flip-flop with differential clock, data input and data output.
The asynchronous Set and Reset controls are edge-triggered rather than level controlled. This allows the user to rapidly set or reset the flip-flop and then continue clocking at the next clock edge, without the necessity of de-asserting the set/reset signal (as would be the case with a level controlled set/reset).
The E431 is also designed with larger internal swings, an approach intended to minimize the time spent crossing the threshold region and thus reduce the metastability susceptibility window.
The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the D and the CLK sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5V below VCC.
•Edge-Triggered Asynchronous Set and Reset
•Differential D, CLK and Q; VBB Reference Available
•1100MHz Min. Toggle Frequency
•Extended 100E VEE Range of ± 4.2V to ± 5.46V
Pinout: 28-Lead PLCC (Top View)
MC10E431
MC100E431
3-BIT DIFFERENTIAL
FLIP-FLOP
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
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VBB |
CLK2 |
CLK2 |
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D2 |
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D2 |
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R2 |
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S2 |
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CLK1 |
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26 |
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Q2 |
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CLK1 |
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17 |
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Q2 |
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R1 |
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28 |
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V |
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VEE |
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1 |
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15 |
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CC |
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Q1 |
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S1 |
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2 |
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Q1 |
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D1 |
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Q0 |
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D1 |
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4 |
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Q0 |
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CLK0 |
CLK0 |
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D0 |
D0 |
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R0 |
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S0 |
VCCO |
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* All VCC and VCCO pins are tied together on the die. |
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PIN NAMES
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Pin |
Function |
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D[0:2], D[0:2] |
Differential Data Inputs |
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CLK[0:2], CLK[0:2] |
Differential Clock |
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S[0:2] |
Edge Triggered Set Inputs |
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R[0:2] |
Edge Triggered Reset Input |
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VBB |
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VBB Reference Output |
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Q[0:2], Q[0:2] |
Differential Data Outputs |
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5/95
Motorola, Inc. 1996
LOGIC DIAGRAM
S0 |
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D0 |
D |
S |
Q0 |
D0 |
Q |
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CLK0 |
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Q |
Q0 |
CLK0 |
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R |
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R0 |
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S1 |
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D1 |
D |
S |
Q1 |
D1 |
Q |
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CLK1 |
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Q |
Q1 |
CLK1 |
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R |
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R1 |
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S2 |
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D2 |
D |
S |
Q2 |
D2 |
Q |
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CLK2 |
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Q |
Q2 |
CLK2 |
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R |
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R2
VBB
REV 3
MC10E431 MC100E431
FUNCTION TABLE
Dn |
CLKn |
Rn |
Sn |
Qn |
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L |
Z |
L |
L |
L |
H |
Z |
L |
L |
H |
X |
X |
Z |
L |
L |
X |
X |
L |
Z |
H |
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Z = Low to high transition
X = Don't Care
DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
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±40°C |
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0°C |
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25°C |
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85°C |
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Symbol |
Characteristic |
Min Typ |
Max |
Min |
Typ |
Max |
Min |
Typ |
Max |
Min |
Typ Max |
Unit |
Cond |
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VBB |
Output Reference |
±1.43 |
±1.30 |
±1.38 |
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±1.27 |
±1.35 |
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±1.25 |
±1.31 |
±1.19 |
V |
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Voltage |
10E |
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100E |
±1.38 |
±1.26 |
±1.38 |
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±1.26 |
±1.38 |
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±1.26 |
±1.38 |
±1.26 |
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IIH |
Input HIGH |
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150 |
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150 |
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150 |
150 |
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μA |
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Current |
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IEE |
Power Supply |
110 |
132 |
110 |
132 |
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110 |
132 |
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110 |
132 |
mA |
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Current |
10E |
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100E |
110 |
132 |
110 |
132 |
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110 |
132 |
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127 |
152 |
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VCMR |
Common Mode |
±1.5 |
0 |
±1.5 |
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0 |
±1.5 |
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0 |
±1.5 |
0 |
V |
1 |
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Range |
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1.VCMR is referenced to the most positive side of the differential input signal. Normal specified operation is obtained when the input signals are within the VCMR range and the input swing is greater than VPP.
AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = VCCO = GND)
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±40°C |
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0°C to 85°C |
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Symbol |
Characteristic |
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Min |
Typ |
Max |
Min |
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Typ |
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Max |
Unit |
Condition |
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fMAX |
Maximum Toggle Frequency |
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1000 |
1400 |
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1100 |
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1400 |
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MHz |
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tPLH |
Propagation Delay to Output |
CLK (Diff) |
410 |
600 |
790 |
450 |
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600 |
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750 |
ps |
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tPHL |
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CLK (SE) |
460 |
600 |
840 |
400 |
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600 |
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800 |
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R |
500 |
725 |
975 |
550 |
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725 |
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925 |
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S |
500 |
725 |
975 |
550 |
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725 |
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925 |
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tS |
Setup Time |
D |
250 |
0 |
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200 |
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0 |
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ps |
1 |
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R |
1100 |
700 |
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1000 |
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700 |
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S |
1100 |
700 |
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1000 |
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700 |
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1 |
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tH |
Hold Time |
D |
250 |
0 |
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200 |
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0 |
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ps |
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tPW |
Minimum Pulse Width |
CLK |
400 |
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400 |
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ps |
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tskew |
Within-Device Skew |
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50 |
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50 |
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ps |
2 |
VPP |
Minimum Input Swing |
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150 |
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150 |
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mV |
3 |
tr/tf |
Rise/Fall Times |
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250 |
450 |
700 |
275 |
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450 |
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650 |
ps |
20±80% |
1.These setup times define the minimum time the CLK or SET/RESET input must wait after the assertion of the RESET/SET input to assure the proper operation of the flip-flop.
2.Within-device skew is defined as identical transitions on similar paths through a device.
3.Minimum input swing for which AC parameters are guaranteed.
MOTOROLA |
2±2 |
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