MC100E337
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
3 Bit Scannable Registered
Bus Transceiver
The MC10E/100E337 is a 3-bit registered bus transceiver with scan. The bus outputs (BUS0±BUS2) are specified for driving a 25Ω bus; the receive outputs (Q0 ± Q2) are specified for 50Ω. The bus outputs feature a normal HIGH level (VOH) and a cutoff LOW level Ð when LOW , the outputs go to ± 2.0V and the output emitter-follower is ªoffº, presenting a high impedance to the bus. The bus outputs also feature edge slow-down capacitors.
•Scannable Version of E336
•25Ω Cutoff Bus Outputs
•50Ω Receiver Outputs
•Scannable Registers
•Sync. and Async. Bus Enables
•Non-inverting Data Path
•1500ps Max. Clock to Bus (Data Transmit)
•1000ps Max. Clock to Q (Data Receive)
•Bus Outputs Feature Internal Edge Slow-Down Capacitors
•Additional Package Ground Pins
•Extended 100E VEE Range of ± 4.2V to ± 5.46V
•75kΩ Input Pulldown Resistors
MC10E337
MC100E337
3-BIT SCANNABLE
REGISTERED
BUS TRANSCEIVER
FN SUFFIX
PLASTIC PACKAGE
CASE 776-02
Both drive and receive sides feature the same logic, including a loopback path to hold data. The HOLD/LOAD function is controlled by Transmit Enable (TEN) and Receive Enable (REN) on the transmit and receive sides respectively, with a HIGH selecting LOAD. Note that the implementation of the E337 Receive Enable differs from that of the E336.
A synchronous bus enable (SBUSEN) is provided for normal, non-scan operation. The asynchronous bus disable (ABUSDIS) disables the bus immediately for scan mode.
The SYNCEN input is provided for flexibility when re-enabling the bus after disabling with ABUSDIS, allowing either synchronous or asynchronous re-enabling. An alternative use is asynchronous-only operation with ABUSDIS, in which case SYNCEN is tied LOW, or left open. SYNCEN is implemented as an overriding SET control (active-LOW) to the enable flip-flop.
Scan mode is selected by a HIGH at the SCAN input. Scan input data is shifted in through S_IN and output data appears at the Q2 output.
All registers are clocked on the positive transition of CLK. Additional lead-frame grounding is provided through the Ground pins (GND) which should be connected to 0V. The GND pins are not electrically connected to the chip.
PIN NAMES
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A0 ± A2 |
Data Inputs A |
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B0 ± B2 |
Data Inputs B |
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S-IN |
Serial (Scan) Data Input |
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TEN, REN |
HOLD/LOAD Controls |
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SCAN |
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Scan Control |
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ABUSDIS |
Asynchronous Bus Disable |
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SBUSEN |
Synchronous Bus Enable |
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SYNCEN |
Synchronous Enable Control |
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CLK |
Clock |
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BUS0 ± BUS2 |
25Ω Cutoff Bus Outputs |
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Q0 ± Q2 |
Receive Data Outputs (Q2 serves as SCAN_OUT in scan mode) |
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12/93 |
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Motorola, Inc. 1996 |
REV 2 |
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MC10E337 MC100E337
Pinout: 28-Lead PLCC (Top View)
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SBUSEN SYNCEN |
B0 |
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A0 ABUSDIS VCCO |
Q0 |
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25 |
24 |
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23 |
22 |
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21 |
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20 |
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SCAN |
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26 |
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18 |
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GND |
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S-IN |
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27 |
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17 |
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BUS0 |
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TEN |
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28 |
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16 |
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VCC |
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VEE |
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1 |
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15 |
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Q1 |
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REN |
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2 |
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14 |
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VCCO |
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CLK |
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3 |
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13 |
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BUS1 |
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A1 |
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4 |
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12 |
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GND |
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5 |
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11 |
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B1 |
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A2 |
B2 |
VCCO |
BUS2 |
GND |
Q2 |
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* All VCC and VCCO pins are tied together on the die. |
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LOGIC DIAGRAM |
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BUS2 |
A2 |
D Q |
D Q |
Q2/ |
B2 |
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SCAN_OUT |
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BUS1 |
A1 |
D Q |
D Q |
Q1 |
B1 |
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BUS0 |
A0 |
D Q |
D Q |
Q0 |
B0 |
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S_IN |
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TEN |
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REN |
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SCAN |
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ABUSDIS |
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SBUSEN |
D Q |
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SYNCEN |
SET |
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CLK |
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MOTOROLA |
2±2 |
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