Motorola MC10E180FN, MC100E180FN Datasheet

PLL	Tuning Circuit
with	2
	IC Bus

The MC44818 is a tuning circuit for TV and VCR tuner applications. It contains, on one chip, all the functions required for PLL control of a VCO. This integrated circuit also contains a high frequency prescaler and thus can handle frequencies up to 1.3 GHz. The MC44818 is a pin compatible drop in replacement for the MC44817, where the only difference is the MC44818 has a fixed divide±by±8 prescaler (cannot be bypassed) and the MC44817 uses the three wire bus.

The MC44818 has a programmable 512/1024 reference divider and is manufactured on a single silicon chip using Motorola's high density bipolar process, MOSAIC (Motorola Oxide Self Aligned Implanted Circuits).

•Complete Single Chip System for MPU Control (I2C Bus). Data and Clock Inputs are 3±Wire Bus Compatible

•Divide±by±8 Prescaler Accepts Frequencies up to 1.3 GHz

•15 Bit Programmable Divider Accepts Input Frequencies up to 165 MHz

•Reference Divider: Programmable for Division Ratios 512 and 1024.

•3±State Phase/Frequency Comparator

•Operational Amplifier for Direct Tuning Voltage Output (30 V)

•Four Integrated PNP Band Buffers for 40 mA (VCC1 to 14.4 V)

•Output Options for the Reference Frequency and the Programmable Divider

•High Sensitivity Preamplifier

•Circuit to Detect Phase Lock

•Fully ESD Protected

MOSAIC is a trademark of Motorola, Inc.

ORDERING INFORMATION

	Operating
Device	Temperature Range	Package
MC44818D	TA = ±20° to +80°C	SO±16

Order this document by MC44818/D

MC44818

TV AND VCR

PLL TUNING CIRCUIT WITH 1.3 GHz PRESCALER AND I2C BUS

SEMICONDUCTOR

TECHNICAL DATA

16

1

D SUFFIX

PLASTIC PACKAGE

CASE 751B (SO±16)

PIN CONNECTIONS

SDA	1			16	AS
SCL	2			15	Lock
XTAL	3			14	VCC3 12 V
Amp In	4			13	B3
VTUN	5			12	B2
VCC2 33 V	6			11	B1
VCC1 5.0 V					B0
	7			10
HF In	8			9	Gnd

(Top View)

Motorola, Inc. 1996

Rev 2

MC44818

Representative Block Diagram

Bands Out 30 mA		V
°	°
(40 mA at 0	to 80 C)	TUN

VCC1

VCC3

VCC2

5.0 V

7

13

12

11

10

14

5

6

12 V

20 k

4

Fout

B

B

B

B

Amp In

Test

3

2

1

0

2.7 V

Fref

Buffers

Logic

Operational

Latches

DTB1

Amplifier

Gnd

9

T13

T9, T12, T14

Phase

15

T10, T11

Comp

Lock

P±On

DTB2

Latches

Fout

Fref

Reset

POR

16

4

6

512/1024

AS

CL

1

I2C Bus

Shift Register

Data

Clock

2

Receiver

Data

15 Bit

Ref

15

RL

Divider

DTF

Latches A

Osc

3

XTAL

Latches B

TDI

HF Input

8

8

Program Divider

Latch Control

Prescaler

15 Bit

Fout

DTS, EN

This device contains 3,204 active transistors.

MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.)

Rating	Pin	Value	Unit
Power Supply Voltage (VCC1)	7	6.0	V
Band Buffer ªOffº Voltage	10±13	14.4	V
Band Buffer ªOnº Current	10±13	50	mA
Band Buffer ± Short Circuit Duration (0 to VCC3) (Note 2)	10±13	Continuous	±
Operational Amplifier Power Supply Voltage (VCC2)	6	40	V
Operational Amplifier Short Circuit Duration (0 to VCC2)	5	Continuous	±
Power Supply Voltage (VCC3)	14	14.4	V
Storage Temperature	±	± 65 to +150	°C
Operating Temperature Range	±	± 20 to +80	°C
Band Buffer Operation (Note 1) at 50 mA each Buffer All	10±13	10	sec
Buffers ªOnº Simultaneously
Operational Amplifier Output Voltage	5	VCC2	V
RF Input Level (10 MHz to 1.3 GHz)	±	1.5	Vrms

NOTES: 1. At VCC3 = VCC1 to 14.4 V and TA = ± 20° to + 80°C.

2. At VCC3 = VCC1 to 14.4 V and TA = ± 20° to + 80°C one buffer ªOnº only.

2	MOTOROLA ANALOG IC DEVICE DATA

MC44818

ELECTRICAL CHARACTERISTICS (VCC1 = 5.0 V, VCC2 = 33 V, VCC3 = 12 V, TA = 25°C, unless otherwise noted.)

Characteristic

Pin

Min

Typ

Max

Unit

VCC1 Supply Voltage Range

7

4.5

5.0

5.5

V

VCC1 Supply Current (VCC1 = 5.0 V)

7

±

37

50

mA

VCC2 Supply Voltage Range

6

25

±

37

V

VCC2 Supply Current (Output Open)

6

±

1.5

2.3

mA

Band Buffer Leakage Current when ªOffº at 12 V

10±13

±

0.01

1.0

μA

Band Buffer Saturation Voltage when ªOnº at 30 mA

10±13

±

0.15

0.3

V

Band Buffer Saturation Voltage when ªOnº at 40 mA

10±13

±

0.2

0.5

V

only for 0° to 80°C

Data/Clock Current at 0 V

1, 2

±10

±

0

μA

Clock Current at 5.0 V

2

0

±

1.0

μA

Data Current at 5.0 V Acknowledge ªOffº

1

0

±

1.0

μA

Data Saturation Voltage at 15 mA Acknowledge ªOnº

1

±

±

1.0

V

Data/Clock Input Voltage Low

1, 2

±

±

1.5

V

Data/Clock Input Voltage High

1, 2

3.0

±

±

V

Clock Frequency Range

2

±

±

100

kHz

Oscillator Frequency Range

3

3.15

3.2

4.05

MHz

Operational Amplifier Internal Reference Voltage

±

2.0

2.75

3.2

V

Operational Amplifier Input Current

4

±15

0

15

nA

DC Open Loop Voltage Gain

±

100

250

±

V/V

Gain Bandwidth Product (CL = 1.0 nF)

±

0.3

±

±

MHz

Vout Low, Sinking 50 μA

5

±

0.2

0.4

V

Vout High, Sourcing 10 μA, VCC2 ± Vout

5

±

0.2

0.5

V

Phase Detector Current in the High Impedance State

4

±15

0

15

nA

Charge Pump High Current of Phase Comparator

4

30

50

85

μA

Charge Pump Low Current of Phase Comparator

4

10

15

30

μA

VCC3 Supply Voltage Range

14

VCC1

±

14.4

V

VCC3 Supply Current

14

mA

All Buffers ªOffº

±

0.2

0.5

One Buffer ªOnº when Open

±

8.0

13

One Buffer ªOnº at 40 mA

±

48

53

Data Format and Bus Receiver

The circuit receives the information for tuning and control

4_STA CA FM FL

CO

BA

STO

via the I2C bus. The incoming information, consisting of a

STA = Start Condition

chip address byte followed by two or four data bytes, is

STO = Stop Condition

treated in the I2C bus receiver. The definition of the

CA = Chip Address Byte

permissible bus protocol is shown below:

CO = Data Byte for Control Information

1_STA

CA

CO

BA

STO

BA = Band Information

FM = Data Byte for Frequency Information

2_STA

CA

FM

FL

STO

FL = Data Byte for Frequency Information

3_STA

CA

CO

BA

FM

FL

STO

Figure 1. Complete Data Transfer Process

SDA

SCL

1±7

8

9

1±7

8

9

1±7

8

9

S

P

STA

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STO

CA

MOTOROLA ANALOG IC DEVICE DATA	3