Motorola MC10E137FN, MC10E137FNR2, MC100E137FN, MC100E137FNR2 Datasheet

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

8 Bit Ripple Counter

The MC10E/100E137 is a very high speed binary ripple counter. The two least significant bits were designed with very fast edge rates while the more significant bits maintain standard ECLinPS output edge rates. This allows the counter to operate at very high frequencies while maintaining a moderate power dissipation level.

•1.8GHz Minimum Count Frequency

•Differential Clock Input and Data Output Pins

•VBB Output for Single-Ended Use

•Internal 75kΩ Input Pulldown Resistors

•Synchronous and Asynchronous Enable Pins

•Asynchronous Master Reset

•Extended 100E VEE Range of ±4.2V to ±5.46V

The device is ideally suited for multiple frequency clock generation as well as a counter in a high performance ATE time measurement board.

Both asynchronous and synchronous enables are available to maximize the device's flexibility for various applications. The asynchronous enable input, A_Start, when asserted enables the counter while overriding any synchronous enable signals. The E137 features XORed enable inputs, EN1 and EN2, which are synchronous to the CLK input. When only one synchronous enable is asserted the counter becomes disabled on the next CLK transition; all outputs remain in the previous state poised for the other synchronous enable or A_Start to be asserted to re-enable the counter. Asserting both synchronous enables causes the counter to become enabled on the next transition of the CLK. If EN1 (or EN2) and CLK edges are coincident, sufficient delay has been inserted in the CLK path (to compensate for the XOR gate delay and the internal D-flip flop setup time) to insure that the synchronous enable signal is clocked correctly, hence, the counter is disabled.

The E137 can also be driven single-endedly utilizing the VBB output supply as the voltage reference for the CLK input signal. If a single-ended signal is to be used the VBB pin should be connected to the CLK input and bypassed to ground via a 0.01μF capacitor. VBB can only source/sink 0.5mA, therefore it should be used as a switching reference for the E137 only.

MC10E137

MC100E137

8-BIT RIPPLE COUNTER

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

PIN NAMES

PIN					FUNCTION


CLK, CLK					Differential Clock Inputs

Q0-Q7, Q0-Q7					Differential Q Outputs
A_Start					Asynchronous Enable Input
EN1, EN2					Synchronous Enable Inputs
MR					Asynchronous Master Reset
VBB					Switching Refernce Output

All input pins left open will be pulled LOW via an input pulldown resistor. Therefore, do not leave the differential CLK inputs open. Doing so causes the current source transistor of the input clock gate to become saturated, thus upsetting the internal bias regulators and jeopardizing the stability of the device.

The asynchronous Master Reset resets the counter to an all zero state upon assertion.

LOGIC DIAGRAM

A_Start

EN1	D	R
EN2		R

		Q
		Q
	CLK	Q
	CLK	Q
	CLK

CLK

VBB

	Q0	Q0		Q1	Q1		Q7	Q7
CLK	Q		CLK	Q		CLK	Q
CLK	Q		CLK	Q		CLK	Q
D			D			D
	R			R			R

7/96

Motorola, Inc. 1996

REV 2

MC10E137 MC100E137

Pinout: 28-Lead PLCC (Top View)

				Q7		Q7	Q6		Q6	VCCO			Q5		Q5

			25		24		23	22		21		20		19
A_Start		26												18		Q4
	EN1	27												17		Q4
	EN1	27												17		Q4
	EN2	28												16		VCC
	EN2	28												16		VCC
		1
	VEE	1												15		Q3
	CLK	2												14		Q3
	CLK	2												14		Q3

	CLK	3												13		Q2
VBB		4												12
VBB		4												12		Q2
			5		6		7	8		9		10		11

				MR	VCCO		Q0
				MR	VCCO		Q0		Q0		Q1		Q1	VCCO
		* All VCC and VCCO pins are tied together on the die.

SEQUENTIAL TRUTH TABLE

Function

EN1

EN2

A_Start

CLK

Reset

Count

Stop

Asynch Start

Count

Stop

Synch Start

Stop

Count

Reset

Z = Low to High Transition

MOTOROLA

2±2

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