MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual J-K Master-Slave
Flip-Flop
The MC10135 is a dual master±slave dc coupled J±K flip±flop. Asynchro± nous set (S) and reset (R) are provided. The set and reset inputs override the clock.
A common clock is provided with separate J±K inputs. When the clock is static, the J±K inputs do not effect the output.
The output states of the flip±flop change on the positive transition of the clock.
PD = 280 mW typ/pkg (No Load)
fTog = 140 MHz typ tpd = 3.0 ns typ
tr, tf = 2.5 ns typ (20%±80%)
LOGIC DIAGRAM
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S1 |
5 |
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2 |
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7 |
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Q1 |
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J1 |
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6 |
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K1 |
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Q1 |
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3 |
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R1 |
4 |
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VCC1 = PIN 1 |
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C |
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9 |
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VCC2 = PIN 16 |
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VEE = PIN 8 |
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S2 |
12 |
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15 |
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10 |
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Q2 |
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J2 |
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K2 11 |
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Q2 |
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14 |
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R2 |
13 |
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R±S TRUTH TABLE |
CLOCK J±K TRUTH TABLE* |
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R |
S |
Qn+1 |
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J |
K |
Qn+1 |
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L |
L |
Qn |
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L |
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L |
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Qn |
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L |
H |
H |
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H |
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L |
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L |
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H |
L |
L |
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L |
H |
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H |
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H |
H |
N.D. |
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H |
H |
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Qn |
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N.D. = Not Defined |
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*Output states change on positive |
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transition of clock for J±K input |
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condition present. |
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MC10135
L SUFFIX
CERAMIC PACKAGE
CASE 620±10
P SUFFIX
PLASTIC PACKAGE
CASE 648±08
FN SUFFIX
PLCC
CASE 775±02
DIP
PIN ASSIGNMENT
VCC1 |
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1 |
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16 |
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VCC2 |
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Q1 |
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2 |
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15 |
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Q2 |
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Q1 |
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3 |
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14 |
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Q2 |
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R1 |
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4 |
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13 |
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R2 |
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S1 |
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5 |
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12 |
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S2 |
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K1 |
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6 |
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11 |
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K2 |
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J1 |
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7 |
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10 |
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J2 |
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VEE |
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8 |
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9 |
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C |
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Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).
3/93
Motorola, Inc. 1996 |
3±22 |
REV 5 |
MC10135
ELECTRICAL CHARACTERISTICS
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Test Limits |
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Pin |
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±30°C |
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+25°C |
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+85°C |
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Under |
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Characteristic |
Symbol |
Test |
Min |
Max |
Min |
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Typ |
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Max |
Min |
Max |
Unit |
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Power Supply Drain Current |
IE |
8 |
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75 |
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54 |
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68 |
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75 |
mAdc |
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Input Current |
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IinH |
6,7,9,10,11 |
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425 |
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265 |
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265 |
μAdc |
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4,5,12,13 |
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620 |
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390 |
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390 |
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IinL |
4,5,6,7,9, |
0.5 |
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0.5 |
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0.3 |
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μAdc |
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10,11,12,13 |
0.5 |
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0.5 |
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0.3 |
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Output Voltage |
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Logic 1 |
VOH |
2 |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
Vdc |
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2 (3.) |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
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Output Voltage |
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Logic 0 |
VOL |
3 |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
Vdc |
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3 (3.) |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
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Threshold Voltage |
Logic 1 |
VOHA |
2 |
±1.080 |
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±0.980 |
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±0.910 |
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Vdc |
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2 (4.) |
±1.080 |
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±0.980 |
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±0.910 |
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Threshold Voltage |
Logic 0 |
VOLA |
3 |
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±1.655 |
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±1.630 |
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±1.595 |
Vdc |
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3 (4.) |
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±1.655 |
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±1.630 |
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±1.595 |
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Switching Times |
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(50Ω Load) |
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ns |
Clock Input |
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Propagation Delay |
t9+2+ |
2 |
1.8 |
5.0 |
1.8 |
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3.0 |
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4.5 |
1.8 |
4.6 |
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t9+2± |
2 |
1.8 |
5.0 |
1.8 |
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3.0 |
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4.5 |
1.8 |
4.6 |
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Rise Time |
(20 to 80%) |
t2+, t3+ |
2, 3 |
1.1 |
4.8 |
1.1 |
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2.0 |
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4.5 |
1.1 |
4.7 |
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Fall Time |
(20 to 80%) |
t2±, t3± |
2, 3 |
1.1 |
4.8 |
1.1 |
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2.0 |
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4.5 |
1.1 |
4.7 |
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Set Input |
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ns |
Propagation Delay |
t5+2+ |
2 |
1.8 |
5.6 |
1.8 |
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3.0 |
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5.0 |
1.8 |
5.2 |
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t12+15+ |
15 |
1.8 |
5.6 |
1.8 |
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3.0 |
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5.0 |
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5.2 |
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t5+3± |
3 |
1.8 |
5.6 |
1.8 |
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3.0 |
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5.0 |
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5.2 |
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t12+14± |
14 |
1.8 |
5.6 |
1.8 |
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3.0 |
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5.0 |
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5.2 |
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Reset Input |
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ns |
Propagation Delay |
t4+2± |
2 |
1.8 |
5.6 |
1.8 |
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3.0 |
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5.0 |
1.8 |
5.2 |
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t4+3± |
3 |
1.8 |
5.6 |
1.8 |
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3.0 |
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5.0 |
1.8 |
5.2 |
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t13+15± |
15 |
1.8 |
5.6 |
1.8 |
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3.0 |
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5.0 |
1.8 |
5.2 |
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t13+14+ |
14 |
1.8 |
5.6 |
1.8 |
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3.0 |
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5.0 |
1.8 |
5.2 |
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Setup Time |
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tsetup |
7 |
2.5 |
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2.5 |
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1.0 |
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2.5 |
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ns |
Hold Time |
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thold |
7 |
1.5 |
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1.5 |
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1.0 |
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2.5 |
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ns |
Toggle Frequency (Max) |
ftog |
2 |
125 |
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125 |
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140 |
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125 |
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MHz |
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1.Individually test each input; apply VIHmax to pin under test.
2.Individually test each input; apply VILmin to pin under test.
3.Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
4.Output level to be measured after a clock pulse has been applied to the CE Input (Pin 6)
VIHmax
VILmin
VIHAmax
VILAmin
MECL Data |
3±23 |
MOTOROLA |
DL122 Ð Rev 6 |
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