MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Hex D Master/Slave Flip-Flop
The MC10176 contains six high-speed, master slave type ªDº flip-flops. Clocking is common to all six flip-flops. Data is entered into the master when the clock is low. Master to slave data transfer takes place on the positive-going Clock transition. Thus, outputs may change only on a positive-going Clock transition. A change in the information present at the data (D) input will not affect the output information any other time due to the master-slave construction of this device.
PD = 460 mW typ/pkg (No Load)
ftoggle= 150 MHz (typ)
tr, tf = 2.0 ns typ (20%±80%)
LOGIC DIAGRAM
D0 |
5 |
2 |
Q0 |
D1 |
6 |
3 |
Q1 |
D2 |
7 |
4 |
Q2 |
D3 |
10 |
13 |
Q3 |
D4 |
11 |
14 |
Q4 |
D5 |
12 |
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15 |
Q5 |
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CLOCK 9
VCC1 = PIN 1
VCC2 = PIN 16
VEE = PIN 8
CLOCKED TRUTH TABLE
C |
D |
Qn+1 |
L |
X |
Qn |
H* |
L |
L |
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H* |
H |
H |
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*A clock H is a clock transition from a low to a high state.
MC10176
L SUFFIX
CERAMIC PACKAGE
CASE 620±10
P SUFFIX
PLASTIC PACKAGE
CASE 648±08
FN SUFFIX
PLCC
CASE 775±02
DIP
PIN ASSIGNMENT
VCC1 |
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1 |
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16 |
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VCC2 |
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Q0 |
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2 |
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15 |
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Q5 |
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Q1 |
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3 |
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14 |
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Q4 |
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Q2 |
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4 |
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13 |
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Q3 |
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D0 |
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5 |
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12 |
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D5 |
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D1 |
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6 |
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11 |
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D4 |
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D2 |
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7 |
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10 |
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D3 |
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VEE |
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8 |
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9 |
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CLOCK |
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Pin assignment is for Dual±in±Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 6±11 of the Motorola MECL Data Book (DL122/D).
3/93
Motorola, Inc. 1996 |
3±131 |
REV 5 |
MC10176
ELECTRICAL CHARACTERISTICS
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Test Limits |
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Pin |
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±30°C |
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+25°C |
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+85°C |
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Under |
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Characteristic |
Symbol |
Test |
Min |
Max |
Min |
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Typ |
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Max |
Min |
Max |
Unit |
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Power Supply Drain Current |
IE |
8 |
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121 |
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88 |
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110 |
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121 |
mAdc |
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Input Current |
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IinH |
5 |
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350 |
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220 |
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220 |
μAdc |
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9 |
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495 |
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310 |
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310 |
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IinL |
5 |
0.5 |
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0.5 |
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0.3 |
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μAdc |
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9 |
0.5 |
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0.5 |
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0.3 |
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Output Voltage |
Logic 1 |
VOH |
2[ |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
Vdc |
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15[ |
±1.060 |
±0.890 |
±0.960 |
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±0.810 |
±0.890 |
±0.700 |
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Output Voltage |
Logic 0 |
VOL |
2[ |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
Vdc |
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15[ |
±1.890 |
±1.675 |
±1.850 |
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±1.650 |
±1.825 |
±1.615 |
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Threshold Voltage |
Logic 1 |
VOHA |
2[ |
±1.080 |
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±0.980 |
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±0.910 |
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Vdc |
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15[ |
±1.080 |
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±0.980 |
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±0.910 |
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Threshold Voltage |
Logic 0 |
VOLA |
2[ |
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±1.655 |
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±1.630 |
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±1.595 |
Vdc |
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15[ |
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±1.655 |
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±1.630 |
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±1.595 |
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Switching Times |
(50Ω Load) |
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ns |
Clock Input |
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Propagation Delay |
t9+2+ |
2 |
1.6 |
4.6 |
1.6 |
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4.5 |
1.6 |
5.0 |
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t9+2± |
2 |
1.6 |
4.6 |
1.6 |
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4.5 |
1.6 |
5.0 |
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Rise Time |
(20 to 80%) |
t2+ |
2 |
1.0 |
4.1 |
1.1 |
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4.0 |
1.1 |
4.4 |
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Fall Time |
(20 to 80%) |
t2± |
2 |
1.0 |
4.1 |
1.1 |
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4.0 |
1.1 |
4.4 |
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Setup Time |
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tsetup |
2 |
2.5 |
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2.5 |
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2.5 |
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ns |
Hold Time |
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thold |
2 |
1.5 |
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1.5 |
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1.5 |
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ns |
Toggle Frequency (Max) |
ftog |
2 |
125 |
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125 |
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150 |
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125 |
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MHz |
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[ Output level to be measured after a clock pulse has been applied to the C Input (Pin 9) 
VIHmax VILmin
MOTOROLA |
3±132 |
MECL Data |
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DL122 Ð Rev 6 |
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