MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1:5 Clock Distribution Chip
The MC100LVEL/100EL14 is a low skew 1:5 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. The LVEL14 is functionally and pin compatible with the EL14 but is designed to operate in ECL or PECL mode for a voltage supply range of ±3.0V to ±3.8V ( or 3.0V to 3.8V). If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01μF capacitor. The VBB output is designed to act as the switching reference for the input of the LVEL14 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current.
The LVEL14 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input.
The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.
•50ps Output-to-Output Skew
•Synchronous Enable/Disable
•Multiplexed Clock Input
•75kΩ Internal Input Pulldown Resistors
•>2000V ESD Protection
•VEE Range of ±3.0V to ±5.5V
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
|
|
|
|
|
|
VCC |
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC |
EN |
NC |
SCLK |
CLK |
CLK |
VBB |
SEL |
VEE |
|||||||||||
20 |
|
19 |
|
|
18 |
|
17 |
|
16 |
|
15 |
|
14 |
|
13 |
|
12 |
11 |
|
|
|
|
|
|
1 |
0 |
|
|
|
|
|
|
|
D |
|
|
|
|
|
|
|
|
|
Q |
|
|
|
|
|
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
Q0 |
Q0 |
Q1 |
Q1 |
Q2 |
Q2 |
Q3 |
Q3 |
Q4 |
Q4 |
MC100LVEL14
MC100EL14
20
1
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D-04
PIN DESCRIPTION
|
PIN |
|
FUNCTION |
|
|
|
|||
|
|
|
|
|
|
CLK |
|
Diff Clock Inputs |
|
|
SCLK |
|
Scan Clock Input |
|
|
EN |
|
|
Sync Enable |
|
SEL |
|
Clock Select Input |
|
|
VBB |
|
Reference Output |
|
|
Q0±4 |
|
Diff Clock Outputs |
|
FUNCTION TABLE
|
|
|
|
|
|
Q |
CLK |
SCLK |
SEL |
|
EN |
||
|
|
|
|
|
|
|
L |
X |
L |
|
L |
L |
|
H |
X |
L |
|
L |
H |
|
X |
L |
H |
|
L |
L |
|
X |
H |
H |
|
L |
H |
|
X |
X |
X |
|
H |
L* |
|
|
|
|
|
|
|
|
*On next negative transition of CLK or SCLK
7/95
Motorola, Inc. 1996 |
4±1 |
REV 1 |
MC100LVEL14 MC100EL14
ABSOLUTE MAXIMUM RATINGS1
Symbol |
|
Characteristic |
Rating |
Unit |
|
|
|
|
|
VEE |
Power Supply (VCC = 0V) |
±8.0 to 0 |
VDC |
|
VI |
Input Voltage (VCC = 0V) |
0 to ±6.0 |
VDC |
|
Iout |
Output Current |
Continuous |
50 |
mA |
|
|
Surge |
100 |
|
|
|
|
|
|
TA |
Operating Temperature Range |
±40 to +85 |
°C |
|
V |
Operating Range1,2 |
|
±5.7 to ±4.2 |
V |
EE |
|
|
|
|
1.Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet.
2.Parametric values specified at: 100EL Series: ±4.20V to ±5.50V
10EL Series: |
±4.94V to ±5.50V |
DC CHARACTERISTICS (V |
EE |
= V |
EE |
(min) ± V |
(max); V |
CC |
= GND1) |
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
EE |
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
±40°C |
|
|
|
0°C to 85°C |
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Symbol |
Characteristic |
|
|
|
|
Min |
|
Typ |
|
|
Max |
|
Min |
|
Typ |
|
Max |
Unit |
Condition |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
VOH |
Output HIGH Voltage |
|
|
|
|
|
±1085 |
|
±1005 |
|
±880 |
|
±1025 |
|
±955 |
|
±880 |
mV |
VIN = VIH(max) |
||
VOL |
Output LOW Voltage |
|
|
|
|
|
±1830 |
|
±1695 |
|
±1555 |
|
±1810 |
|
±1705 |
|
±1620 |
mV |
or VIL(min) |
||
VOHA |
Output HIGH Voltage |
|
|
|
|
|
±1095 |
|
Ð |
|
|
Ð |
|
±1035 |
|
Ð |
|
Ð |
mV |
VIN = VIH(max) |
|
VOLA |
Output LOW Voltage |
|
|
|
|
|
Ð |
|
Ð |
|
|
±1555 |
|
Ð |
|
Ð |
|
±1610 |
mV |
or VIL(min) |
|
VIH |
Input HIGH Voltage |
|
|
|
|
|
±1165 |
|
Ð |
|
|
±880 |
|
±1165 |
|
Ð |
|
±880 |
mV |
|
|
VIL |
Input LOW Voltage |
|
|
|
|
|
±1810 |
|
Ð |
|
|
±1475 |
|
±1810 |
|
Ð |
|
±1475 |
mV |
|
|
IIL |
Input LOW Current |
|
|
|
|
|
±300 |
|
Ð |
|
|
Ð |
|
±300 |
|
Ð |
|
Ð |
μA |
VIN = VIL(max) |
|
|
|
CLK |
|
|
|
|
|
|
|||||||||||||
|
|
|
|
Others |
0.5 |
|
|
|
|
|
|
0.5 |
|
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
1.This table replaces the three tables traditionally seen in ECL 100K data books. The same DC parameter values at VEE = ±4.5V now apply across the full VEE range of ±3.0V to ±5.5V. Outputs are terminated through a 50Ω resistor to ±2.0V except where otherwise specified on the individual data sheets.
MOTOROLA |
4±2 |
ECLinPS and ECLinPS Lite |
|
|
DL140 Ð Rev 3 |
Loading...