MC100LVE310FNR2
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
4–1
REV 0.1
Motorola, Inc. 1996
7/95
Low V oltage 2:8 Dif fer ential
Fanout Buffer
ECL/PECL Compatible
The MC100LVE310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device features
fully differential clock paths to minimize both device and system skew.
The LVE310 offers two selectable clock inputs to allow for redundant or
test clocks to be incorporated into the system clock trees. The
MC100E310 is pin compatible to the National 100310 device. The
MC100LVE310 works from a –3.3V supply while the MC100E310
provides identical function and performance from a standard –4.5V 100E
voltage supply.
• Dual Differential Fanout Buffers
• 200ps Part–to–Part Skew
• 50ps Output–to–Output Skew
• Low Voltage ECL/PECL Compatible
• 28–lead PLCC Packaging
For applications which require a single–ended input, the V
BB
reference
voltage is supplied. For single–ended input applications the V
BB
reference should be connected to the CLK input and bypassed to ground
via a 0.01µf capacitor. The input signal is then driven into the CLK input.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50Ω, even if only
one side is being used. In most applications all nine differential pairs will
be used and therefore terminated. In the case where fewer than nine
pairs are used it is necessary to terminate at least the output pairs
adjacent to the output pair being used in order to maintain minimum skew.
Failure to follow this guideline will result in small degradations of
propagation delay (on the order of 10–20ps) of the outputs being used,
while not catastrophic to most designs this will result in an increase in
skew. Note that the package corners isolate outputs from one another
such that the guideline expressed above holds only for outputs on the
same side of the package.
The MC100L VE310, as with most ECL devices, can be operated from a positive V
CC
supply in PECL mode. This allows the
LVE310 to be used for high performance clock distribution in +3.3V systems. Designers can take advantage of the LVE310’s
performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line
terminations are typically used as they require no additional power supplies, if parallel termination is desired a terminating voltage
of V
CC
–2.0V will need to be provided. For more information on using PECL, designers should refer to Motorola Application Note
AN1406/D.
MC100L VE310
MC100E310
LOW VOLTAGE
2:8 DIFFERENTIAL
FANOUT BUFFER
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02
MC100LVE310 MC100E310
MOTOROLA ECLinPS and ECLinPS Lite
DL140 — Rev 3
4–2
1
567891011
25 24 23 22 21 20 19
26
27
28
2
3
4
18
17
16
15
14
13
12
V
EE
CLK_SEL
CLKa
V
CC
CLKa
V
BB
CLKb
Q3
Q3
Q4
V
CCO
Q4
Q5
Q5
Pinout: 28–Lead PLCC
(Top View)
Q0 Q0 Q1 V
CCO
Q1 Q2 Q2
CLKb Q7 Q6NC V
CCO
Q7 Q6
PIN NAMES
Function
Differential Input Pairs
Differential Outputs
V
BB
Output
Input Clock Select
Pins
CLKa, CLKb
Q0:7
V
BB
CLK_SEL
Input Clock
CLKa Selected
CLKb Selected
CLK_SEL
0
1
LOGIC SYMBOL
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
V
BB
CLKa
CLKa
Q4
Q4
Q5
Q5
Q6
Q6
Q7
Q7
CLKb
CLKb
CLK_SEL
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