MC100EPT25
Differential LVECL/ECL to LVTTL Translator
The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, ±3.3V to ±5.2V, and ground. The small outline 8±lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal.
The VBB output allows the EPT25 to also be used in a single±ended input mode. In this mode the VBB output is tied to the D input for a non±inverting buffer or the D input for an inverting buffer. If used, the VBB pin should be bypassed to ground via a 0.01mF capacitator.
•1.1ns Typical Propagation Delay
•275MHz Fmax (Clock bit stream, not pseudo±random)
•Differential LVECL/ECL inputs
•Small Outline SOIC Package
•24mA TTL outputs
•Flow Through Pinouts
•Internal Input Resistors: Pulldown on D, Pulldown and Pullup on D
•Q Output will default LOW with inputs open or at GND
•ESD Protection: >4000V HBM, >200V MM
•VBB Output
•New Differential Input Common Mode Range
•Moisture Sensitivity Level 1, Indefinite Time Out of Drypack. For Additional Information, See Application Note AND8003/D
•Flammability Rating: UL±94 code V±0 @ 1/8º, Oxygen Index 28 to 34
•Transistor Count = 111 devices
VEE |
1 |
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8 |
VCC |
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LVTTL |
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D |
2 |
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7 |
Q |
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MARKING |
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DIAGRAMS* |
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8 |
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SO±8 |
HPT25 |
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8 |
D SUFFIX |
ALYW |
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1 |
CASE 751 |
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1 |
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8 |
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8 |
TSSOP±8 |
HR25 |
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DT SUFFIX |
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ALYW |
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1 |
CASE 948R |
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1 |
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A |
= Assembly Location |
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L |
= Wafer Lot |
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Y |
= Year |
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W = Work Week
*For additional information, see Application Note AND8002/D
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PIN DESCRIPTION |
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PIN |
FUNCTION |
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Q |
LVTTL Output |
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D, |
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Differential LVECL Input Pair |
D |
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VCC |
Positive Supply |
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VBB |
Output Reference Voltage |
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GND |
Ground |
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VEE |
Negative Supply |
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D |
3 |
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6 |
NC |
ORDERING INFORMATION |
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LVECL |
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Device |
Package |
Shipping |
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MC100EPT25D |
SO±8 |
98 Units / Rail |
VBB |
4 |
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5 |
GND |
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MC100EPT25DR2 |
SO±8 |
2500 / Reel |
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MC100EPT25DT |
TSSOP±8 |
98 Units / Rail |
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Figure 1. 8±Lead Pinout |
(Top View) and Logic Diagram |
MC100EPT25DTR2 |
TSSOP±8 |
2500 / Reel |
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Semiconductor Components Industries, LLC, 2000 |
1 |
Publication Order Number: |
May, 2000 ± Rev. 1 |
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MC100EPT25/D |
MC100EPT25
MAXIMUM RATINGS*
Symbol |
Parameter |
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Value |
Unit |
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VCC |
Power Supply (Referenced to GND, VEE = ±3.3V) |
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0 to 3.8 |
VDC |
VEE |
Power Supply (Referenced to GND, VCC = +3.3V) |
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±6.0 to 0 |
VDC |
VI |
Input Voltage (VI not more positive than GND) |
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0 to 3.8 |
VDC |
Iout |
Output Current |
Continuous |
50 |
mA |
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Surge |
100 |
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IBB |
VBB Sink/Source Current{ |
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± 0.5 |
mA |
TA |
Operating Temperature Range |
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±40 to +85 |
°C |
Tstg |
Storage Temperature |
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±65 to +150 |
°C |
θJA |
Thermal Resistance (Junction±to±Ambient) |
Still Air |
190 |
°C/W |
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500lfpm |
130 |
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θJC |
Thermal Resistance (Junction±to±Case) |
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41 to 44 ± 5% |
°C/W |
Tsol |
Solder Temperature (<2 to 3 Seconds: 245°C desired) |
265 |
°C |
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* Maximum Ratings are those values beyond which damage to the device may occur.
{ Use for inputs of same package only.
DC CHARACTERISTICS, ECL/LVECL (VCC = +3.3V; VEE = ±5.5V to ±3.0V, GND = 0V)
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±40°C |
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25°C |
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85°C |
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Symbol |
Characteristic |
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Min |
Typ |
Max |
Min |
Typ |
Max |
Min |
Typ |
Max |
Unit |
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IEE |
Power Supply Current |
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8.0 |
16 |
25 |
8.0 |
16 |
25 |
8.0 |
16 |
25 |
mA |
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(Note 1.) |
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VIH |
Input HIGH Voltage Single Ended |
±1165 |
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±880 |
±1165 |
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±880 |
±1165 |
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±880 |
mV |
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(Note 4.) |
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VIL |
Input LOW Voltage Single Ended |
±1810 |
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±1625 |
±1810 |
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±1625 |
±1810 |
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±1625 |
mV |
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(Note 4.) |
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VBB |
Output Voltage Reference |
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±1550 |
±1450 |
±1350 |
±1550 |
±1450 |
±1350 |
±1550 |
±1450 |
±1350 |
mV |
VIHCMR |
Input HIGH Voltage Common Mode |
VEE+2.0 |
0.0 |
VEE+2.0 |
0.0 |
VEE+2.0 |
0.0 |
V |
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Range (Note 3.) |
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IIH |
Input HIGH Current |
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150 |
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150 |
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150 |
μA |
IIL |
Input LOW Current |
D |
0.5 |
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0.5 |
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0.5 |
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μA |
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D |
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±150 |
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±150 |
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±150 |
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NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
1.(VCC = +3.3V, GND = 0V, VEE = ±3.3V), all other pins floating.
2.All loading with 500 ohms to GND, CL = 20pF.
3.VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC.
4.Input and output parameters vary 1:1 with VCC.
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2
MC100EPT25
TTL OUTPUT DC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V; VEE = ±3.3V ± 0.3V; TA = ±40°C to 85°C)
Symbol |
Characteristic |
Min |
Typ |
Max |
Unit |
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ICCH |
Power Supply Current (Outputs set to HIGH) |
6.0 |
10 |
14 |
mA |
ICCL |
Power Supply Current (Outputs set to LOW) |
7.0 |
12 |
17 |
mA |
VOH |
Output HIGH Voltage (IOH = ±3.0mA) (Note 5.) |
2.2 |
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V |
VOL |
Output LOW Voltage (IOL = 24mA) (Note 5.) |
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0.5 |
V |
IOS |
Output Short Circuit Current |
±130 |
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±60 |
mA |
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained.
5. All loading with 500 ohms to GND, CL = 20pF.
AC CHARACTERISTICS (VCC = 3.3V ± 0.3V; GND = 0V)
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±40°C |
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25°C |
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85°C |
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Symbol |
Characteristic |
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Min |
Typ |
Max |
Min |
Typ |
Max |
Min |
Typ |
Max |
Unit |
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fmax |
Maximum Toggle Frequency |
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275 |
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275 |
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275 |
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MHz |
tPLH, |
Propagation Delay to |
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800 |
1200 |
1800 |
800 |
1100 |
1600 |
800 |
1100 |
1600 |
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tPHL |
Output Differential |
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tSK+ + |
Output±to±Output Skew++ |
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60 |
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60 |
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60 |
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ps |
tSK± ± |
Output±to±Output Skew± ± |
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25 |
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25 |
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25 |
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tSKPP |
Part±to±Part Skew (Note 6.) |
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500 |
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500 |
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500 |
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tJITTER |
Cycle±to±Cycle Jitter |
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TBD |
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TBD |
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TBD |
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ps |
VPP |
Input Voltage Swing |
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100 |
800 |
1200 |
100 |
800 |
1200 |
100 |
800 |
1200 |
mV |
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(Differential) (Note 7.) |
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Output Rise/Fall Times |
Q, |
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450 |
600 |
750 |
450 |
600 |
750 |
450 |
600 |
750 |
ps |
Q |
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tf |
(0.8V ± 2.0V) |
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900 |
1160 |
1400 |
900 |
1100 |
1400 |
900 |
1100 |
1400 |
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6.Skews are measured between outputs under identical conditions.
7.200mV input guarantees full logic swing at the output.
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