TP13064A |
TP3064A, TP3067A, TP13064A, TP13067A |
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MONOLITHIC SERIAL INTERFACE |
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COMBINED PCM CODEC AND FILTER |
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SCTS025C ± SEPTEMBER 1992 ±REVISED JULY 1996 |
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DComplete PCM Codec and Filtering Systems Include:
±Transmit High-Pass and Low-Pass Filtering
±Receive Low-Pass Filter With (sin x)/x Correction
±Active RC Noise Filters
±μ-Law or A-Law Compatible Coder and
Decoder
±Internal Precision Voltage Reference
±Serial I/O Interface
±Internal Autozero Circuitry
Dμ-Law ± TP3064B and TP13064B
DA-Law ± TP3067B and TP13067B
D± 5-V Operation
DLow Operating Power . . . 70 mW Typ
DPower-Down Standby Mode . . . 3 mW Typ
DAutomatic Power Down
DTTLor CMOS-Compatible Digital Interface
DMaximizes Line Interface Card Circuit Density
DImproved Versions of National Semiconductor TP3064, TP3067, TP3064-X, TP3067-X
description
The TP3064A, TP3067A, TP13064A, and TP13067A are comprised of a single-chip PCM codec (pulse-code-modulated encoder and decoder) and PCM line filter. These devices provide all the functions required to interface a full-duplex (2-wire) voice telephone circuit with a TDM (time-division-multiplexed) system. These devices are pin-for-pin compatible with the National Semiconductor TP3064A and TP3067A, respectively. Primary applications include:
•Line interface for digital transmission and switching of T1 carrier, PABX, and central office telephone systems
•Subscriber line concentrators
•Digital-encryption systems
•Digital voice-band data-storage systems
•Digital signal processing
DW OR N PACKAGE
(TOP VIEW)
VPO+ |
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20 |
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VBB |
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ANLG GND |
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VFXI+ |
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VPO± |
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VFXI± |
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VPI |
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GSX |
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VFRO |
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ANLG LOOP |
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VCC |
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TSX |
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FSR |
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FSX |
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DR |
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DX |
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BCLKR/CLKSEL |
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BCLKX |
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MCLKR/PDN |
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MCLKX |
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These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be used at the analog termination of a PCM line or trunk. The devices require two transmit and receive master clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive frame-sync pulses. The TP3064A, TP3067A, TP13064A, and TP13067A provide the band-pass filtering of the analog signals prior to encoding and after decoding of voice and call progress tones. The TP3067A and TP13067A contain patented circuitry to achieve low transmit channel idle noise and are not recommended for applications in which the composite signals on the transmit side are below ±55 dBm0.
The TP3064A and TP3067A are characterized for operation from 0°C to 70°C. The TP13064A and TP13067A are characterized for operation from ±40°C to 85°C.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the CMOS gates.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
TP3064A, TP3067A, TP13064A, TP13067A MONOLITHIC SERIAL INTERFACE COMBINED PCM CODEC AND FILTER
SCTS025C ± SEPTEMBER 1992 ±REVISED JULY 1996
functional block diagram
VFXI ±
VFXI +
VPO+
VPO ±
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R2 |
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Analog |
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GSX |
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Input |
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16 ANLG |
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R1 |
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LOOP |
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Autozero |
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± |
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Logic |
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19 |
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+ |
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R |
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RC |
Switched- |
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S/H |
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Active Filter |
Capacitor |
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DAC |
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Band-Pass Filter |
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+ |
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R |
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Voltage |
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A/D |
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Transmit |
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Reference |
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Control |
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Regulator |
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Logic |
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DX |
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Comparator |
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OE |
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Switched- |
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R3 |
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RC Active |
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S/H |
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Receive |
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Capacitor |
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4 VPI |
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Filter |
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DAC |
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Regulator |
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Low-Pass Filter |
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DR |
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CLK |
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R4 |
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5 VFRO |
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Timing and Control |
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5 V |
± 5 V |
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TSX |
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VCC |
VBB |
ANLG GND |
MCLKX |
MCLKR/ |
BCLKX |
BCLKR/ |
FSR |
FSX |
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PDN |
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CLKSEL |
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2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C ± SEPTEMBER 1992 ±REVISED JULY 1996
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Terminal Functions |
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TERMINAL |
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DESCRIPTION |
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NAME |
NO. |
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ANLG GND |
2 |
Analog ground. All signals are referenced to ANLG GND. |
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ANLG LOOP |
16 |
Analog loopback control input. Must be set to logic low for normal operation. When pulled to logic high, the transmit |
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filter input is disconnected from the output of the transmit preamplifier and connected to VPO+ of the receive power |
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amplifier. |
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BCLKR/CLKSEL |
9 |
The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately, |
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can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode. |
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BCLKX is used for both transmit and receive directions (see Table 1). |
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BCLKX |
12 |
The bit clock that shifts out the PCM data on DX. BCLKX can vary from 64 kHz to 2.048 MHz, but must be synchronous |
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with MCLKX. |
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DR |
8 |
Receive data input. PCM data is shifted into DR following the FSR leading edge. |
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DX |
13 |
The 3-state PCM data output that is enabled by FSX. |
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FSR |
7 |
Receive frame sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see Figures |
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1 and 2 for timing details). |
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FSX |
14 |
Transmit frame sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see |
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Figures 1 and 2 for timing details). |
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GSX |
17 |
Analog output of the transmit input amplifier. GSX is used to externally set gain. |
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MCLKR/PDN |
10 |
Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should |
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be synchronous for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal |
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timing. When MCLKR is connected continuously high, the device is powered down. |
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MCLKX |
11 |
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR |
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15 |
Open-drain output that pulses low during the encoder time slot |
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TSX |
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VBB |
20 |
Negative power supply. VBB = ± 5 V ± 5% |
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VCC |
6 |
Positive power supply. VCC = 5 V ± 5% |
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VFRO |
5 |
Analog output of the receive filter |
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VFXI+ |
19 |
Noninverting input of the transmit input amplifier |
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VFXI ± |
18 |
Inverting input of the transmit input amplifier |
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VPI |
4 |
Inverting input to the receive power amplifier. Also powers down both amplifiers when connected to VBB |
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VPO+ |
1 |
The noninverted output of the receive power amplifier |
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VPO ± |
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The inverted output of the receive power amplifier |
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C ± SEPTEMBER 1992 ±REVISED JULY 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . |
. . . . . . . . . . . 7 |
V |
Supply voltage, VBB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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. . . . . . . . . ±7 V |
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Voltage range at any analog input or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. VCC + 0.3 V to VBB ± 0.3 |
V |
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Voltage range at any digital input or output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
VCC + 0.3 V to GND ± 0.3 |
V |
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Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
See Dissipation Rating Table |
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Operating free-air temperature range, TA: TP3064A, TP3067A . . . . . . . . . . . . |
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. . 0°C to 70°C |
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TP13064A, TP13067A . . . . . . . . . . |
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±40°C to 85°C |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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±65°C to 150°C |
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Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . |
. . . . . . . 260°C |
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²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
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DISSIPATION RATING TABLE |
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PACKAGE |
TA ≤ 25°C |
DERATING FACTOR |
TA = 70°C |
TA = 85°C |
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POWER RATING |
ABOVE TA = 25°C |
POWER RATING |
POWER RATING |
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DW |
1025 mW |
8.2 mW/°C |
656 mW |
533 mW |
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N |
1150 mW |
9.2 mW/°C |
736 mW |
598 mW |
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recommended operating conditions (see Note 2)
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MIN |
NOM |
MAX |
UNIT |
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Supply voltage, VCC |
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4.75 |
5 |
5.25 |
V |
Supply voltage, VBB |
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± 4.75 |
± 5 |
± 5.25 |
V |
High-level input voltage, VIH |
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2.2 |
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V |
Low-level input voltage, VIL |
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0.6 |
V |
Common-mode input voltage range, VICR³ |
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± 2.5 |
V |
Load resistance at GSX, RL |
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10 |
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kΩ |
Load capacitance at GSX, CL |
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50 |
pF |
Operating free-air temperature, TA |
TP3064A, TP3067A |
0 |
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70 |
°C |
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TP13064A, TP13067A |
± 40 |
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85 |
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³ Measure with CMRR > 60 dB.
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device power-up sequence paragraphs later in this document should be followed.
4 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C ± SEPTEMBER 1992 ±REVISED JULY 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
supply current
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PARAMETER |
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TEST CONDITIONS |
TP306xA |
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TP1306xA |
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UNIT |
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MIN TYP² |
MAX |
MIN TYP² |
MAX |
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ICC |
Supply current from VCC |
Power down |
No load |
0.5 |
1 |
0.5 |
1.2 |
mA |
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Active |
6 |
10 |
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11 |
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IBB |
Supply current from VBB |
Power down |
No load |
0.5 |
1 |
0.5 |
1.2 |
mA |
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Active |
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10 |
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11 |
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² All typical values are at VCC = 5 V, VBB = ± 5 V, and TA = 25°C.
electrical characteristics at VCC = 5 V ± 5%, VBB = ±5 V ± 5%, GND at 0 V, TA = 25°C (unless otherwise noted)
digital interface
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PARAMETER |
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TEST CONDITIONS |
MIN MAX |
UNIT |
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VOH |
High-level output voltage |
DX |
IH = ± 3.2 mA |
2.4 |
V |
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VOL |
Low-level output voltage |
DX |
IL = 3.2 mA |
0.4 |
V |
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TSX |
IL = 3.2 mA, Drain open |
0.4 |
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IIH |
High-level input current |
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VI = VIH to VCC |
± 10 |
μA |
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IIL |
Low-level input current |
All digital inputs |
VI = GND to VIL |
± 10 |
μA |
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IOZ |
Output current in high-impedance state |
DX |
VO = GND to VCC |
± 10 |
μA |
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analog interface with transmit amplifier input
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PARAMETER |
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TEST CONDITIONS |
MIN |
TYP² |
MAX |
UNIT |
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II |
Input current |
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VFXI+ or VFXI± |
VI = ± 2.5 V to 2.5 V |
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± 200 |
nA |
ri |
Input resistance |
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VFXI+ or VFXI± |
VI = ± 2.5 V to 2.5 V |
10 |
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MΩ |
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ro |
Output resistance |
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Closed loop, Unit gain |
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3 |
Ω |
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Output dynamic range |
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GSX |
RL ≥ 10 kΩ |
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V |
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AV |
Open-loop voltage amplification |
VFXI+ to GSX |
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5000 |
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BI |
Unity-gain bandwidth |
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GSX |
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1 |
2 |
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MHz |
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VIO |
Input offset voltage |
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VFXI+ or VFXI± |
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± 20 |
mV |
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CMRR |
Common-mode rejection ratio |
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60 |
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dB |
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kSVR |
Supply-voltage rejection ratio |
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60 |
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dB |
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² All typical values are at V |
CC |
= 5 V, V |
BB |
= ± 5 V, and T = 25°C. |
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A |
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analog interface with receive filter
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PARAMETER |
TEST CONDITIONS |
MIN |
TYP² |
MAX |
UNIT |
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Output resistance |
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VFRO |
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1 |
3 |
Ω |
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Load resistance |
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VFRO = ± 2.5 V |
600 |
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Ω |
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Load capacitance |
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VFRO to GND |
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500 |
pF |
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Output dc offset voltage |
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VFRO to GND |
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± 200 |
mV |
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² All typical values are at VCC = 5 V, VBB = ± 5 V, and TA = 25°C.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
5 |
TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C ± SEPTEMBER 1992 ±REVISED JULY 1996
analog interface with power amplifiers
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PARAMETER |
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TEST CONDITIONS |
MIN TYP² MAX |
UNIT |
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II |
Input current |
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VPI = ± 1 V to 1 V |
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nA |
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ri |
Input resistance |
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VPI = ± 1 V to 1 V |
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10 |
MΩ |
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ro |
Output resistance |
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VPO+ or VPO± |
Inverting unity gain |
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1 |
Ω |
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AV |
Voltage amplification |
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VPO± or VPO+ |
VPO ± = 1.77 Vrms, |
RL = 600 Ω |
± 1 |
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BI |
Unity-gain bandwidth |
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VPO± |
Open loop |
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400 |
kHz |
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VIO |
Input offset voltage |
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± 25 |
mV |
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kSVR |
Supply-voltage rejection ratio of VCC or VBB |
VPO ± connected to VPI |
0 kHz to 4 kHz |
60 |
dB |
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4 kHz to 50 kHz |
36 |
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RL |
Load resistance |
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Connected from VPO+ to VPO ± |
600 |
Ω |
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CL |
Load capacitance |
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100 |
pF |
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² All typical values are at V |
CC |
= 5 V, V |
BB |
= ± 5 V, and T = 25°C. |
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A |
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6 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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