Texas Instruments TLV5627IPWR, TLV5627IPW, TLV5627IDR, TLV5627ID, TLV5627CPWR Datasheet

TLV5627C, TLV5627I 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS232 ± JUNE1999

DFour 8-Bit D/A Converters

DProgrammable Settling Time of 3 μs or 9 μs Typ

DTMS320, (Q)SPI, and Microwire Compatible Serial Interface

DLow Power Consumption:

7 mW, Slow Mode ± 5-V Supply

3 mW, Slow Mode ± 3-V Supply

DReference Input Buffers

DMonotonic Over Temperature

DDual 2.7-V to 5.5-V Supply (Separate Digital and Analog Supplies)

DHardware Power Down

DSoftware Power Down

DSimultaneous Update

applications

DBattery Powered Test Instruments

DDigital Offset and Gain Adjustment

DIndustrial Process Controls

DMachine and Motion Control Devices

DArbitrary Waveform Generation

description

D OR PW PACKAGE

(TOP VIEW)

The TLV5627 is a four channel, 8-bit voltage	DVDD								AVDD
output digital-to-analog converter (DAC) with a						1	16
flexible 4-wire serial interface. The 4-wire serial			PD			2	15		REFINAB
interface allows glueless interface to TMS320,		LDAC				3	14		OUTA
SPI, QSPI, and Microwire serial ports. The		DIN				4	13		OUTB
TLV5627 is programmed with a 16-bit serial word		SCLK				5	12		OUTC
comprised of a DAC address, individual DAC			CS			6	11		OUTD
control bits, and an 8-bit DAC value.			FS			7	10		REFINCD
The device has provision for two supplies: one	DGND					8	9		AGND
digital supply for the serial interface (via pins

DVDD and DGND), and one for the DACs,

reference buffers and output buffers (via pins AVDD and AGND). Each supply is independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3-V supply (also used on pins DVDD and DGND), with the DACs operating on a 5-V supply. The digital and analog supplies can be tied together.

The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode make it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage than DACs C and D.

The device, implemented with a CMOS process, is available in 16-terminal SOIC and TSSOP packages. The TLV5627C is characterized for operation from 0°C to 70°C. The TLV5627I is characterized for operation from ±40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS232 ± JUNE1999

AVAILABLE OPTIONS

		PACKAGE
TA
	SOIC		TSSOP
	(D)		(PW)
0°C to 70°C	TLV5627CD		TLV5627CPW
± 40°C to 85°C	TLV5627ID		TLV5627IPW

functional block diagram
						AVDD	DVDD
15						16	1
REFINAB
				DAC A
						+
		Power-On				_	x2		14
		Reset							OUTA
					8	8-Bit	8
						DAC
		Serial	10	10-Bit		Latch
	4
DIN		Input		Data
		Register		and
		2		Control	2	2-Bit
				Register		Control	2
						Data	Power Down/
	7					Latch
FS		DAC					Speed Control
	5
SCLK		Select/
		Control
	6
CS		Logic
						DAC B		13	OUTB
						DAC C		12	OUTC
REFINCD
						DAC D		11	OUTD
						3	2
		9	8
		AGND	DGND			LDAC	PD

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

								TLV5627C, TLV5627I
						2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS
								WITH POWER DOWN
								SLAS232 ± JUNE1999
							Terminal Functions
		TERMINAL			I/O			DESCRIPTION
		NAME		NO.
	AGND			9		Analog ground
	AVDD			16		Analog supply
				6	I	Chip select. This terminal is active low.
	CS
	DGND			8		Digital ground
	DIN			4	I	Serial data input
	DVDD			1		Digital supply
	FS			7	I	Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out
						to the TLV5627.
				2	I	Power-down pin. Powers down all DACs (overriding their individual power down settings), and all output stages.
	PD
						This terminal is active low.
				3	I	Load DAC. When the		signal is high, no DAC output updates occur when the input digital data is read into
	LDAC						LDAC
						the serial interface. The DAC outputs are only updated when LDAC is low.
	REFINAB			15	I	Voltage reference input for DACs A and B.
	REFINCD			10	I	Voltage reference input for DACs C and D.
	SCLK			5	I	Serial clock input
	OUTA			14	O	DAC A output
	OUTB			13	O	DAC B output
	OUTC			12	O	DAC C output
	OUTD			11	O	DAC D output

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage, (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . 7	V
Supply voltage difference, (AVDD to DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±2.8 V to 2.8	V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to DVDD + 0.3	V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to AVDD + 0.3	V
Operating free-air temperature range, TA: TLV5627C . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 0°C to 70°C
TLV5627I . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS232 ± JUNE1999

recommended operating conditions

			MIN	NOM	MAX	UNIT
	Supply voltage, AVDD, DVDD	5-V supply	4.5	5	5.5	V
		3-V supply	2.7	3	3.3
	High-level digital input, VIH	DVDD = 2.7 V to 5.5 V	2			V
	Low-level digital input, VIL	DVDD = 2.7 V to 5.5 V			0.8	V
	Reference voltage, Vref to REFINAB, REFINCD terminal	5-V supply (see Note 1)	0	2.048	AVDD±1.5	V
		3-V supply (see Note 1)	0	1.024	AVDD±1.5
	Load resistance, RL		2	10		kW
	Load capacitance, CL				100	pF
	Serial clock rate, SCLK				20	MHz
	Operating free-air temperature	TLV5627C	0		70	°C
		TLV5627I	±40		85

NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

static DAC specifications

	PARAMETER	TEST CONDITIONS	MIN TYP	MAX	UNIT
	Resolution		8		bits
	Integral nonlinearity (INL), end point adjusted	See Note 2	±0.3	±0.5	LSB
	Differential nonlinearity (DNL)	See Note 3	±0.03	±0.5	LSB
EZS	Zero scale error (offset error at zero scale)	See Note 4		±10	mV
	Zero scale error temperature coefficient	See Note 5	10		ppm/°C
EG	Gain error	See Note 6		±0.6	%of FS
					voltage
	Gain error temperature coefficient	See Note 7	10		ppm/°C

NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.

3.The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

4.Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

5.Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) ± EZS (Tmin)]/Vref × 106/(Tmax ± Tmin).

6.Gain error is the deviation from the ideal output (2Vref ± 1 LSB) with an output load of 10 kW excluding the effects of the zero-error.

7.Gain temperature coefficient is given by: EG TC = [EG(Tmax) ± EG (Tmin)]/Vref × 106/(Tmax ± Tmin).

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLV5627C, TLV5627I 2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS232 ± JUNE1999

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)

individual DAC output specifications

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VO	Voltage output	RL = 10 kΩ	0		AVDD±0.1	V
	Output load regulation accuracy	RL = 2 kΩ vs 10 kΩ		0.1	0.25	% of FS
						voltage

reference input (REFINAB, REFINCD)

	PARAMETER	TEST CONDITIONS		MIN TYP	MAX	UNIT
VI	Input voltage range	See Note 8		0	AVDD±1.5	V
RI	Input resistance			10		MΩ
CI	Input capacitance			5		pF
	Reference feed through	REFIN = 1 Vpp at 1 kHz + 1.024 V dc		±75		dB
		(see Note 9)
	Reference input bandwidth	REFIN = 0.2 Vpp + 1.024 V dc	Slow	0.5		MHz
			Fast	1

NOTES: 8. Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.

9.Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref(REFINAB or REFINCD) input = 1.024 Vdc + 1 Vpp at 1 kHz.

digital inputs (D0±D11, CS, WEB, LDAC, PD)

	PARAMETER	TEST CONDITIONS	MIN TYP	MAX	UNIT
IIH	High-level digital input current	VI = DVDD		±1	μA
IIL	Low-level digital input current	VI = 0 V		±1	μA
CI	Input capacitance		3		pF

power supply

		PARAMETER			TEST CONDITIONS		MIN TYP	MAX	UNIT
				5-V supply,	No load, Clock running	Slow	1.4	2.2	mA
	IDD	Power supply current				Fast	3.5	5.5
				3-V supply,	No load, Clock running	Slow	1	1.5	mA
						Fast	3	4.5
		Power down supply current, See Figure 12					1		μA
	PSRR	Power supply rejection ratio	Zero scale gain	See Notes 10 and 11			± 68		dB
			Gain				± 68

10.Zero-scale-error rejection ratio (EZS±RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.5 V dc, and measuring the proportion of this signal imposed on the zero-code output voltage.

11.Gain-error rejection ratio (EG-RR) is measured by varying the AVDD from 5 ±0.5 V and 3 ±0.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TLV5627C, TLV5627I

2.7-V TO 5.5-V 8-BIT 4-CHANNEL DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS232 ± JUNE1999

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)

analog output dynamic performance

	PARAMETER		TEST CONDITIONS			MIN TYP	MAX	UNIT
SR	Output slew rate	CL = 100 pF,	RL = 10 kW,		Fast	5		V/ms
		VO = 10% to 90%,
					Slow	1		V/ms
		Vref = 2.048 V, 1024 V
ts	Output settling time	To ± 0.1 LSB,	CL = 100 pF,		Fast	2.5	4	ms
		RL = 10 kW,	See Notes 12 and 14		Slow	8.5	18
ts(c)	Output settling time, code to code	To ± 0.1 LSB,	CL = 100 pF,		Fast	1		ms
		RL = 10 kW,	See Notes 13 and 14		Slow	2
	Glitch energy	Code transition from 7F0 to 800				10		nV-sec
SNR	Signal-to-noise ratio	Sinewave generated by DAC,				57
S/(N+D)	Signal to noise + distortion					49
		Reference voltage = 1.024 at 3 V and 2.048 at 5 V,						dB
THD	Total harmonic distortion	fs = 400 KSPS, fOUT = 1.1 kHz sinewave,				±50
		CL = 100 pF,	RL = 10 kΩ, BW = 20 kHz
SFDR	Spurious free dynamic range					60

NOTES: 12. Settling time is the time for the output signal to remain within ± 0.1 LSB of the final measured value for a digital input code change of 0x020 to 0xFF0 or 0xFF0 to 0x020.

13.Settling time is the time for the output signal to remain within ± 0.1 LSB of the final measured value for a digital input code change of one count.

14.Limits are ensured by design and characterization, but are not production tested.

digital input timing requirements

							MIN NOM MAX	UNIT
	tsu(CS±FS)	Setup time,		low before FS↓			10	ns
			CS
	tsu(FS±CK)	Setup time, FS low before first negative SCLK edge					8	ns
	tsu(C16±FS)	Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising					10	ns
		edge of FS
		Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before			CS	rising
	tsu(C16±CS)	edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup					10	ns
		time is between the FS rising edge and CS rising edge.
	twH	Pulse duration, SCLK high					25	ns
	twL	Pulse duration, SCLK low					25	ns
	tsu(D)	Setup time, data ready before SCLK falling edge					8	ns
	th(D)	Hold time, data held valid after SCLK falling edge					5	ns
	twH(FS)	Pulse duration, FS high					20	ns

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265