Texas Instruments TMX320VC5410PGE-80, TMX320VC5410GGW120, TMX320VC5410GGW100, TMS320VC5410PGE100, TMS320VC5410GGW100 Datasheet

C

F 2 A A C

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus

40-Bit Arithmetic Logic Unit (ALU) Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators

17- ×17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation

Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator

Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle

Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

Data Bus With a Bus Holder Feature

Extended Addressing Mode for 8M × 16-Bit

Maximum Addressable External Program Space

64K x 16-Bit On-Chip RAM Composed of:

±Four Blocks of 2K × 16-Bit On-Chip

Dual-Access Program/Data RAM

±Seven Blocks of 8K × 16-Bit On-Chip

Single-Access Program/Data RAM

16K × 16-Bit On-Chip ROM Configured to

Program Memory

Enhanced External Parallel Interface (XIO2)

Single-Instruction-Repeat and Block-Repeat Operations for Program Code

Block-Memory-Move Instructions for Better Program and Data Management

Instructions With a 32-Bit Long Word Operand

description

Instructions With Twoor Three-Operand Reads

Arithmetic Instructions With Parallel Store and Parallel Load

Conditional Store Instructions

Fast Return From Interrupt

On-Chip Peripherals

±Software-Programmable Wait-State Generator and Programmable Bank-Switching

±On-Chip Programmable Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source

±One 16-Bit Timer

±Six-Channel Direct Memory Access (DMA) Controller

±Three Multichannel Buffered Serial Ports (McBSPs)

±8-Bit Enhanced Parallel Host-Port Interface (HPI8)

Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1² (JTAG) Boundary Scan Logic

144-Pin Thin Quad Flatpack (TQFP) (PGE Suffix)

176-Pin Ball Grid Array (BGA) (GGW Suffix)

10-ns and 8.3-ns Single-Cycle Fixed-Point Instruction Execution Time (100 and 120 MIPS)

3.3-V I/O and 2.5-V Core Supply Voltages

The TMS320VC5410 fixed-point, digital signal processor (DSP) (hereafter referred to as the '5410 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

² IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

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,*! %"% -%)(, *!+ -$!	-!+',	)" !0 , (,-+.'!(-, ,- ( +				/ ++ (-1
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					POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443		1

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

description (continued)

Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. The '5410 also includes the control mechanisms to manage interrupts, repeated operations, and function calls.

NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).

PGE PACKAGE²³

(TOP VIEW)

														SS				A21				DD				A9					A8				A7				A6				A5					A4				HD6				A3				A2					A1				A0				DD				HDS2					SS				HDS1				SS				DD				HD5				D15				D14				D13				HD4				D12			D11				D10				D9				D8				D7				D6				DD				SS				A20				A19
													V									CV																																																			DV							V										V				CV																																																			DV				V
				VSS						144							143				142				141				140					139				138				137				136					135				134				133				132					131					130			129				128						127			126				125				124				123				122				121				120				119				118			117				116				115				114				113				112				111				110		109								A18
										1																																																																																																																																																108
				A22						2																																																																																																																																																107								A17
				VSS						3																																																																																																																																																106								VSS
			DVDD							4																																																																																																																																																105								A16
				A10						5																																																																																																																																																104								D5
				HD7						6																																																																																																																																																103								D4
				A11						7																																																																																																																																																102								D3
				A12						8																																																																																																																																																101								D2
				A13						9																																																																																																																																																100								D1
				A14						10																																																																																																																																																99								D0
				A15						11																																																																																																																																																98								RS
			CVDD							12																																																																																																																																																97								X2/CLKIN
				HAS						13																																																																																																																																																96								X1
				VSS						14																																																																																																																																																95								HD3
				VSS						15																																																																																																																																																94								CLKOUT
			CVDD							16																																																																																																																																																93								VSS
				HCS						17																																																																																																																																																92								HPIENA
				HR/W						18																																																																																																																																																91								CVDD
		READY
										19																																																																																																																																																90								VSS
				PS
										20																																																																																																																																																89								TMS
				DS						21																																																																																																																																																88								TCK
				IS						22																																																																																																																																																87								TRST
				R/W						23																																																																																																																																																86								TDI
		MSTRB								24																																																																																																																																																85								TDO
	IOSTRB									25																																																																																																																																																84								EMU1/OFF
				MSC						26																																																																																																																																																83								EMU0
				XF						27																																																																																																																																																82								TOUT
			HOLDA							28																																																																																																																																																81								HD2
				IAQ						29																																																																																																																																																80								NC
				HOLD						30																																																																																																																																																79								CLKMD3
				BIO						31																																																																																																																																																78								CLKMD2
			MP/MC							32																																																																																																																																																77								CLKMD1
			DVDD							33																																																																																																																																																76								VSS
				VSS						34																																																																																																																																																75								DVDD
				BDR1						35																																																																																																																																																74								BDX1
			BFSR1							36																																																																																																																																																73								BFSX1
										37							38				39				40				41					42				43				44				45					46				47				48				49					50					51			52				53						54			55				56				57				58				59				60				61				62				63			64				65				66				67				68				69				70				71		72
											V							BCLKR1				HCNTL0				V					BCLKR0				BCLKR2				BFSR0				BFSR2					BDR0				HCNTL1				BDR2				BCLKX0					BCLKX2								HINT				CV					BFSX0				BFSX2				HRDY				DV				V				HD0				BDX0				BDX2				IACK				HBIL NMI							INT0				INT1				INT2				INT3				CV				HD1				V				BCLKX1		V
																																																																					V
														SS												SS																																											SS								DD																	DD				SS																																											DD								SS								SS
² V	and DV							are power supplies for I/O pins while V																																																												SS					and CV																				are power supplies for core CPU.
SS				DD																																																																																		DD

³ The McBSP pins BCLKS0, BCLKS1, and BCLKS2 are not available on the PGE package.

The pin assignments table lists each signal and pin number for the TMS320VC5410PGE (144-pin) package. The terminal functions table lists each terminal name, function, and operating mode for the TMS320VC5410.

2	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

description (continued)

GGW PACKAGE (BOTTOM VIEW)

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

1	3	5	7	9	11	13	15	17
2	4	6	8	10	12		14	16

The pin assignments table lists each signal and pin number for the TMS320VC5410GGW (176-pin) package. The terminal functions table lists each terminal name, function, and operating modes for the TMS320VC5410.

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

3

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

Pin Assignments for the TMS320VC5410PGE (144-Pin Package) and the TMS320VC5410GGW (176-Pin Package)

PIN NAME

PGE

GGW

PIN NAME

PGE

GGW

PIN NO.

PIN NO.

PIN NO.

PIN NO.

VSS

1

B1

BFSR1

36

R2

A22

2

C2

CVDD

T1

VSS

3

C1

VSS

37

U2

DVDD

4

D3

BCLKR1

38

T3

CVDD

D2

HCNTL0

39

U3

A10

5

D1

VSS

40

R4

HD7

6

E3

DVDD

T4

VSS

E2

BCLKR0

41

U4

A11

7

E1

BCLKR2

42

R5

A12

8

F3

BFSR0

43

T5

A13

9

F2

BCLKS0

U5

A14

10

F1

BFSR2

44

R6

A15

11

G4

BDR0

45

T6

DVDD

G3

VSS

U6

CVDD

12

G2

HCNTL1

46

P7

13

G1

BDR2

47

R7

HAS

VSS

14

H1

CVDD

T7

VSS

15

H4

BCLKX0

48

U7

CVDD

16

H3

BCLKX2

49

U8

17

H2

BCLKS2

P8

HCS

18

J1

VSS

50

R8

HR/W

READY

19

J4

51

T8

HINT

20

J3

CVDD

52

U9

PS

21

J2

BFSX0

53

P9

DS

VSS

K1

BFSX2

54

R9

22

K2

HRDY

55

T9

IS

23

K4

DVDD

56

U10

R/W

DVDD

K3

VSS

57

T10

24

L1

HD0

58

P10

MSTRB

25

L2

BDX0

59

R10

IOSTRB

CVDD

L3

CVDD

U11

26

L4

BDX2

60

T11

MSC

XF

27

M1

61

R11

IACK

28

M2

VSS

P11

HOLDA

29

M3

HBIL

62

U12

IAQ

30

N1

63

T12

HOLD

NMI

31

N2

64

R12

BIO

INT0

32

N3

65

U13

MP/MC

INT1

DVDD

33

P1

DVDD

T13

VSS

34

P2

66

R13

INT2

BCLKS1

P3

67

U14

INT3

BDR1

35

R1

CVDD

68

T14

HD1

69

R14

CVDD

D17

VSS

70

U15

A16

105

D16

4	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

Pin Assignments for the TMS320VC5410PGE (144-Pin Package) and the TMS320VC5410GGW (176-Pin Package) (Continued)

PIN NAME

PGE

GGW

PIN NAME

PGE

GGW

PIN NO.

PIN NO.

PIN NO.

PIN NO.

BCLKX1

71

T15

VSS

106

D15

VSS

72

U16

A17

107

C17

CVDD

T17

A18

108

C16

BFSX1

73

R16

DVDD

B17

BDX1

74

R17

CVDD

A16

DVDD

75

P15

A19

109

B15

VSS

76

P16

A20

110

A15

CLKMD1

77

P17

VSS

111

C14

CLKMD2

78

N15

DVDD

112

B14

CLKMD3

79

N16

D6

113

A14

NC

80

N17

D7

114

C13

HD2

81

M15

D8

115

B13

TOUT

82

M16

D9

116

A13

EMU0

83

M17

D10

117

C12

VSS

L14

D11

118

B12

EMU1/OFF

84

L15

DVDD

A12

TDO

85

L16

D12

119

D11

TDI

86

L17

HD4

120

C11

87

K17

VSS

B11

TRST

TCK

88

K14

D13

121

A11

TMS

89

K15

D14

122

A10

VSS

90

K16

D15

123

D10

CVDD

91

J17

HD5

124

C10

HPIENA

92

J14

CVDD

125

B10

VSS

93

J15

VSS

126

A9

DVDD

J16

127

D9

HDS1

CLKOUT

94

H17

VSS

128

C9

HD3

95

H16

129

B9

HDS2

X1

96

H14

DVDD

130

A8

X2/CLKIN

97

H15

A0

131

B8

98

G17

A1

132

D8

RS

VSS

G16

CVDD

C8

D0

99

G15

A2

133

A7

D1

100

G14

A3

134

B7

DVDD

F17

DVDD

C7

D2

101

F16

HD6

135

D7

D3

102

F15

A4

136

A6

VSS

E17

VSS

B6

D4

103

E16

A5

137

C6

D5

104

E15

A6

138

A5

DVDD

B5

DVDD

C4

A7

139

C5

CVDD

142

A3

A8

140

A4

A21

143

B3

A9

141

B4

VSS

144

A2

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

5

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

terminal functions

The terminal functions table lists each signal, function, and operating mode(s) grouped by function.

			Terminal Functions
TERMINAL		I/O²	DESCRIPTION
	NAME
			DATA SIGNALS
A22	(MSB)	O/Z	Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The sixteen LSB
A21			lines, A0 to A15, are multiplexed to address external memory (program, data) or I/O. The seven MSB lines, A16
A20			to A22, address external program space memory. A22±A0 is placed in the high-impedance state in the hold
A19			mode. A22±A0 also goes into the high-impedance state when OFF is low.
A18
A17			The address bus has a bus holder feature that eliminates passive components and the power dissipation
A16			associated with them. The bus holder keeps the address bus at the previous logic level when the bus goes into
A15			a high-impedance state.
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0	(LSB)
D15	(MSB)	I/O/Z	Parallel data bus D15 (MSB) through D0 (LSB). D15±D0 is multiplexed to transfer data between the core CPU
D14			and external data/program memory or I/O devices. D15±D0 is placed in high-impedance state when not
D13			outputting data or when RS or HOLD is asserted. D15±D0 also goes into the high-impedance state when	OFF
D12			is low.
D11
D10			The data bus has a bus holder feature that eliminates passive components and the power dissipation associated
D9			with them. The bus holder keeps the data bus at the previous logic level when the bus goes into a
D8			high-impedance state. The bus holders on the data bus can be enabled/disabled under software control.
D7
D6
D5
D4
D3
D2
D1
D0	(LSB)

² I = Input, O = Output, Z = High-impedance, S = Supply

6	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

Terminal Functions (Continued)

TERMINAL

I/O²

DESCRIPTION

NAME

INITIALIZATION, INTERRUPT AND RESET OPERATIONS

Interrupt acknowledge signal.

IACK

indicates receipt of an interrupt and that the program counter is fetching the

IACK

O/Z

interrupt vector location designated by A15±A0. IACK also goes into the high-impedance state when OFF is low.

INT0

INT1

I

External user interrupt inputs.

INT0±INT3 is prioritized and is maskable by the interrupt mask register (IMR) and

INT2

interrupt mode bit. INT0 ±INT3 can be polled and reset by way of the interrupt flag register (IFR).

INT3

I

Nonmaskable interrupt.

NMI

is an external interrupt that cannot be masked by way of the INTM or the IMR. When

NMI

NMI is activated, the processor traps to the appropriate vector location.

Reset.

RS

causes the digitial signal processor (DSP) to terminate execution and forces the program counter to

RS

I

0FF80h. When RS is brought to a high level, execution begins at location 0FF80h of program memory. RS affects

various registers and status bits.

causes

Microprocessor/microcomputer mode select pin. If active low at reset (microcomputer mode), MP/MC

the internal program ROM to be mapped into the upper 16K words of program memory space. In the

MP/MC

I

microprocessor mode, off-chip memory and its corresponding addresses (instead of internal program ROM) are

accessed by the DSP.

MULTIPROCESSING SIGNALS

Branch control. A branch can be conditionally executed when

BIO

is active. If low, the processor executes the

BIO

I

conditional instruction. The

BIO

condition is sampled during the decode phase of the pipeline for the XC

instruction, and all other instructions sample

BIO

during the read phase of the pipeline.

External flag output (latched software-programmable signal). XF is set high by the SSBX XF instruction, set low

XF

O/Z

by RSBX XF instruction or by loading ST1. XF is used for signaling other processors in multiprocessor

configurations or used as a general-purpose output pin. XF goes into the high-impedance state when OFF is

low, and is set high at reset.

MEMORY CONTROL SIGNALS

Data, program, and I/O space select signals.

DS,

PS,

and

IS

are always high unless driven low for

DS

communicating to a particular external space. Active period corresponds to valid address information. DS, PS,

PS

O/Z

and IS are placed into the high-impedance state in the hold mode; these signals also go into the high-impedance

IS

state when OFF is low.

Memory strobe signal.

MSTRB

is always high unless low-level asserted to indicate an external bus access to

MSTRB

O/Z

data or program memory. MSTRB is placed in the high-impedance state in the hold mode; it also goes into the

high-impedance state when OFF is low.

Data ready. READY indicates that an external device is prepared for a bus transaction to be completed. If the

READY

I

device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the

processor performs ready detection if at least two software wait states are programmed. The READY signal is

not sampled until the completion of the software wait states.

Read/write signal. R/W

indicates transfer direction during communication to an external device. R/W is normally

R/W

O/Z

in the read mode (high), unless it is asserted low when the DSP performs a write operation. R/W is placed in

the high-impedance state in the hold mode; and it also goes into the high-impedance state when

OFF

is low.

I/O strobe signal.

IOSTRB

is always high unless low-level asserted to indicate an external bus access to an I/O

IOSTRB

O/Z

device. IOSTRB is placed in the high-impedance state in the hold mode; it also goes into the high-impedance

state when OFF is low.

Hold input.

HOLD

is asserted to request control of the address, data, and control lines. When acknowledged by

HOLD

I

the 'VC5410, these lines go into the high-impedance state.

Hold acknowledge.

HOLDA

indicates to the external circuitry that the processor is in a hold state and that the

HOLDA

O/Z

address, data, and control lines are in the high-impedance state, allowing them to be available to the external

circuitry. HOLDA also goes into the high-impedance state when OFF is low.

Microstate complete.

MSC

goes low when the last wait state of two or more internal software wait states

MSC

O/Z

programmed is executed. If connected to the READY line, MSC forces one external wait state after the last

internal wait state has been completed. MSC also goes into the high-impedance state when OFF is low.

² I = Input, O = Output, Z = High-impedance, S = Supply

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

7

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

				Terminal Functions (Continued)
	TERMINAL		I/O²			DESCRIPTION
		NAME
				MEMORY CONTROL SIGNALS (CONTINUED)
				Instruction acquisition signal.	IAQ	is asserted (active low) when there is an instruction address on the address
	IAQ		O/Z
				bus and goes into the high-impedance state when OFF is low.
				OSCILLATOR/TIMER SIGNALS
				Clock output signal. CLKOUT can represent the machine-cycle rate of the CPU divided by 1, 2, 3, or 4 as
	CLKOUT		O/Z	configured in the bank-switching control register (BSCR). Following reset, CLKOUT represents the
				machine-cycle rate divided by 4.
	CLKMD1			Clock mode select signals. CLKMD1 ± CLKMD3 allows the selection and configuration of different clock modes
	CLKMD2		I
				such as crystal, external clock, PLL mode.
	CLKMD3
	X2/CLKIN		I	Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock input.
	X1		O	Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
				unconnected. X1 does not go into the high-impedance state when OFF is low.
	TOUT		O	Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is one CLKOUT
				cycle wide. TOUT also goes into the high-impedance state when OFF is low.
		MULTICHANNEL BUFFERED SERIAL PORT 0 (McBSP #0), MULTICHANNEL BUFFERED SERIAL PORT 1 (McBSP #1),
				AND MULTICHANNEL BUFFERED SERIAL PORT 2 (McBSP #2) SIGNALS
	BCLKR0
	BCLKR1		I/O/Z	Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.
	BCLKR2
	BDR0
	BDR1		I	Serial data receive input
	BDR2
	BFSR0
	BFSR1		I/O/Z	Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BDR.
	BFSR2
	BCLKX0			Transmit clock. BCLKX serves as the serial shift clock for the McBSP transmitter. BCLKX can be configured as
	BCLKX1		I/O/Z	an input or an output, and is configured as an input following reset. BCLKX enters the high-impedance state when
	BCLKX2			OFF goes low.
	BDX0
				Serial data transmit output. BDX is placed in the high-impedance state when not transmitting, when RS is
	BDX1		O/Z
				asserted, or when OFF is low.
	BDX2
	BFSX0			Frame synchronization pulse for transmit input/output. The BFSX pulse initiates the data transmit process over
	BFSX1		I/O/Z	BDX. BFSX can be configured as an input or an output, and is configured as an input following reset. BFSX goes
	BFSX2			into the high-impedance state when OFF is low.
	BCLKS0			Serial port clock reference. The McBSP can be programmed to use either BCLKS or the CPU clock as a
	BCLKS1		I	reference for generation of internal clock and frame sync signals. Pins with internal pullup devices.
	BCLKS2			NOTE: These pins are not available on the PGE package.
				MISCELLANEOUS SIGNAL
	NC			No connection
				HOST-PORT INTERFACE SIGNALS
				Parallel bidirectional data bus. HD0±HD7 is placed in the high-impedance state when not outputting data. The
				signals go into the high-impedance state when OFF is low. The HPI data bus has a feature called a bus holder
	HD0±HD7		I/O/Z	that eliminates passive components and the power dissipation associated with them. The bus holder keeps the
				data bus at the previous logic level when the bus goes into high-impedance state. The bus holder on the HPI
				data bus can be enabled/disabled under software control.

² I = Input, O = Output, Z = High-impedance, S = Supply

8	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

Terminal Functions (Continued)

TERMINAL

I/O²

DESCRIPTION

NAME

HOST-PORT INTERFACE SIGNALS (CONTINUED)

HCNTL0

I

Control inputs

HCNTL1

HBIL

I

Byte identification

I

Chip select

HCS

HDS1

I

Data strobe

HDS2

I

Address strobe

HAS

I

Read/write

HR/W

HRDY

O/Z

Ready output. HRDY goes into the high-impedance state when

OFF

is low.

Interrupt output. When the DSP is in reset,

is driven high.

goes into the high-impedance state when

HINT

HINT

HINT

O/Z

OFF is low.

HPI module select. HPIENA must be tied to DVDD to have HPI selected. If HPIENA is left open or connected

HPIENA

I

to ground, the HPI module is not selected, internal pullup for the HPI input pins are enabled, and the HPI data

bus has holders set. HPIENA is provided with an internal pulldown resistor that is active only when RS is low.

HPIENA is sampled when RS goes high and is ignored until RS goes low again.

SUPPLY PNS

VSS

S

Ground. Dedicated power supply for the core CPU.

CVDD

S

+VDD. Dedicated power supply for the core CPU.

DVDD

S

+VDD. Dedicated power supply for I/O pins.

TEST PINS

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes

TCK

I

on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction register,

or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur on the

falling edge of TCK.

TDI

I

IEEE standard 1149.1 test data input. Pin with internal pullup device. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK.

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) are shifted out

TDO

O/Z

of TDO on the falling edge of TCK. TDO is in the high-impedance state except when the scanning of data is in

progress. TDO also goes into the high-impedance state when OFF is low.

TMS

I

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into

the TAP controller on the rising edge of TCK.

IEEE standard 1149.1 test reset.

TRST,

when high, gives the IEEE standard 1149.1 scan system control of the

TRST

I

operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and

the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown device.

Emulator 0 pin. When

TRST

is driven low, EMU0 must be high for activation of the

OFF

condition. When

TRST

EMU0

I/O/Z

is driven high, EMU0 is used as an interrupt to or from the emulator system and is defined as input/output by

way of the IEEE standard 1149.1 scan system.

Emulator 1 pin/disable all outputs. When

TRST

is driven high, EMU1/OFF

is used as an interrupt to or from the

emulator system and is defined as input/output by way of IEEE standard 1149.1 scan system. When TRST is

driven low, EMU1/OFF is configured as OFF. The EMU1/OFF signal, when active low, puts all output drivers into

the high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for

EMU1/OFF

I/O/Z

multiprocessing applications). Therefore, for the OFF condition, the following apply:

TRST = low,

EMU0 = high

EMU1/OFF = low

² I = Input, O = Output, Z = High-impedance, S = Supply

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9

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

architecture

The 'VC5410 DSP implements the standard 'C54x CPU which uses an advanced, modified Harvard architecture that maximizes processing power by maintaining three separate bus structures for data memory and one for program memory. Separate program and data spaces allow simultaneous access to program instructions and data, providing a high degree of parallelism. For example, two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the 'VC5410 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

For detailed information on the architecture of the C5000 family of DSPs, refer to the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).

memory

The 'VC5410 device provides both on-chip ROM and RAM memories to aid in system performance and integration.

on-chip ROM with bootloader

The 'VC5410 features a 16K-word × 16-bit on-chip maskable ROM that can only be mapped into program memory space.

Customers can arrange to have the ROM of the 'VC5410 programmed with contents unique to any particular application.

A bootloader is available in the standard 'VC5410 on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. If MP/MC of the device is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard 'VC5410 devices provide different ways to download the code to accomodate various system requirements:

Parallel from 8-bit or 16-bit-wide EPROM

Parallel from I/O space, 8-bit or 16-bit mode

Serial boot from serial ports, 8-bit or 16-bit mode

Host-port interface boot

Warm boot

10	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

on-chip ROM with bootloader (continued)

The standard on-chip ROM layout is shown in Table 1.

	Table 1. Standard On-Chip ROM Layout²
ADDRESS RANGE	DESCRIPTION
C000h±D4FFh	ROM tables for the GSM EFR speech codec
D500h±D6FFh	256-point complex radix-2 DIT FFT with looped code
D700h±DCFFh	FFT twiddle factors for a 256-point complex radix-2 FFT
DD00h±DEFFh	1024-point complex radix-2 DIT FFT with looped code
DF00h±F7FFh	FFT twiddle factors for a 1024-point complex radix-2 FFT
F800h±FBFFh	Bootloader
FC00h±FCFFh	-Law expansion table
FD00h±FDFFh	A-Law expansion table
FE00h±FEFFh	Sine look-up table
FF00h±FF7Fh	Reserved²
FF80h±FFFFh	Interrupt vector table

²In the 'VC5410 ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h±FF7Fh in program space.

on-chip RAM

The 'VC5410 device contains 8K words ×16-bit on-chip dual-access RAM (DARAM) and 56K words × 16-bit of on-chip single-access RAM (SARAM).

The DARAM is composed of four blocks of 2K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. The DARAM is located in the address range 0080h±1FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one.

The SARAM is composed of seven blocks of 8K words each. Each of these seven blocks is a single-access memory. For example, an instruction word can be fetched from one SARAM block in the same cycle as a data word is written to another SARAM block. The SARAM located in the address range 2000h±7FFFh in data space can be mapped into program space by setting the OVLY bit to one, while the SARAM located in the address range 18000h±1FFFFh in program space can be mapped into data space by setting the DROM bit to one.

on-chip memory security

The 'VC5410 device has a maskable option to protect the contents of on-chip memories. When the ROM protect bit is set, no externally originating instruction can access the on-chip memory spaces. In addition, when the ROM protect option is enabled, HPI8 read access is limited to address range 0001000h ± 0001FFFh. Data located outside this range cannot be read through the HPI8. Write access to the entire HPI8 memory map is still maintained.

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

11

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

memory map

Hex 0000

007F

0080

1FFF

2000

7FFF

8000

FF7F

FF80

FFFF

	Program		Hex	Program
	Reserved		010000
	(OVLY = 1)
	External
	(OVLY = 0)
				Mapped to
	On-Chip
				Lower Page 0
	DARAM			(OVLY = 1)
	(OVLY = 1)			External
	External			(OVLY = 0)
	(OVLY = 0)
	On-Chip
	SARAM1
	(OVLY = 1)
	External
	(OVLY = 0)		017FFF
			018000

External

External

Interrupts and

Reserved

(External)

01FFFF

Page 0

Page 1

MP/MC= 1

(Microprocessor Mode)

Hex	Program		Hex			Program
0000		010000
	Reserved
	(OVLY = 1)
	External
	(OVLY = 0)
007F						Mapped to
0080
	On-Chip
						Lower Page 0
	DARAM					(OVLY = 1)
	(OVLY = 1)					External
	External
						(OVLY = 0)
	(OVLY = 0)
1FFF
2000	On-Chip
	SARAM1
	(OVLY = 1)
	External
7FFF	(OVLY = 0)	017FFF
8000	External	018000
BFFF						On-Chip
C000
	On-Chip					SARAM2
	ROM
	(16K Words)
FF7F
FF80	Interrupts and
	Reserved
	(On-Chip ROM)	01FFFF
FFFF
	Page 0					Page 1
		MP/MC=		0
	(Microcomputer Mode)

Figure 1. Memory Map

Hex	Data
0000	Memory-Mapped
005F	Registers
0060	Scratch-Pad
007F	RAM
0080
	On-Chip
	DARAM
	(8K Words)
1FFF
2000
	On-Chip
	SARAM1
	(24K Words)
7FFF
8000

On-Chip

SARAM2 (DROM = 1)

External (DROM = 0)

FFFF

program memory

Software can configure their memory cells to reside inside or outside of the program address map. When the cells are mapped into program space, the device automatically accesses them when their addresses are within bounds. When the program-address generation (PAGEN) logic generates an address outside its bounds, the device automatically generates an external access. The advantages of operating from on-chip memory are as follows:

Higher performance because no wait states are required

Lower cost than external memory

Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

12	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

relocatable interrupt vector table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft Ð meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words, either two 1-word instructions or one 2-word instruction, are reserved at each vector location to accommodate a delayed branch instruction which allows branching to the appropriate interrupt service routine without the overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page.

NOTE: The hardware reset (RS) vector cannot be remapped because the hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

extended program memory

The 'VC5410 uses a paged extended memory scheme in program space to allow access of up to 8192K of program memory. In order to implement this scheme, the 'VC5410 includes several features which are also present on 'C548/549:

Twenty-three address lines, instead of sixteen

An extra memory-mapped register, the XPC

Six extra instructions for addressing extended program space

Program memory in the 'VC5410 is organized into 128 pages that are each 64K in length, as shown in Figure 2.

00 0000		01 0000		02 0000		. . .	7F 0000
	Page 0		Page 1		Page 2			Page 127
	64K		64K		64K			64K
	Words		Words		Words			Words
00 FFFF		01 FFFF		02 FFFF		. . .	7F FFFF
	XPC = 0		XPC = 1		XPC = 2			XPC=127

Figure 2. Extended Program Memory

(On-Chip RAM Not Mapped in Program Space and Data Space, OVLY = 0)

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13

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

extended program memory (continued)

When the on-chip RAM is enabled in program space, each page of program memory is made up of two parts: a common block of 32K words and a unique block of 32K words. The common block is shared by all pages and each unique block is accessible only through its assigned page. Figure 3 shows the common and unique blocks.

xx 0000	Page 0
xx 7FFF	32K² Words
	On-Chip
	XPC = xx
00 8000				02 8000			7F 8000
		01 8000
	Page 0		Page 1		Page 2	. . .		Page 127
	32K Words		32K Words		32K Words			32K Words
	External		On-Chip		External	. . .		External
00 FFFF		01 FFFF		02 FFFF			7F FFFF
	XPC = 0		XPC = 1		XPC = 2			XPC=127

² See Figure 1 for more information about this on-chip memory region.

NOTE A: When the on-chip RAM is enabled in program space, all accesses to the region xx 0000 ± xx 7FFF, regardless of page number, are mapped to the on-chip RAM at 00 0000 ± 00 7FFF.

Figure 3. Extended Program Memory

(On-Chip RAM Mapped in Program Space and Data Space, OVLY = 1)

If the on-chip ROM is enabled (MP/MC = 0), it is enabled only on page 0. It is not mapped to any other page in program memory.

The value of the XPC register defines the page selection. This register is memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.

To facilitate page-switching through software, the 'VC5410 has six special instructions that affect the XPC:

FB[D] pmad (23 bits) ± Far branch

FBACC[D] Accu[22:0] ± Far branch to the location specified by the value in accumulator A or accumulator B

FCALL[D] pmad (23 bits) ± Far call

FCALA[D] Accu[22:0] ± Far call to the location specified by the value in accumulator A or accumulator B

FRET[D] ± Far return

FRETE[D] ± Far return with interrupts enabled

In addition to these new instructions, two '54x instructions are extended to use 23 bits in the 'VC5410:

READA data_memory (using 23-bit accumulator address)

WRITA data_memory (using 23-bit accumulator address)

All other instructions, software and hardware interrupts do not modify the XPC register and access only memory within the current page.

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TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

data memory

The data memory space addresses up to 64K of 16-bit words. The device automatically accesses the on-chip RAM when addressing within its bounds. When an address is generated outside the RAM bounds, the device automatically generates an external access.

The advantages of operating from on-chip memory are as follows:

Higher performance because no wait states are required

Higher performance because of better flow within the pipeline of the central arithmetic logic unit (CALU)

Lower cost than external memory

Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space.

on-chip peripherals

The 'VC5410 device has the following peripherals:

Software-programmable wait-state generator

Programmable bank-switching

A host-port interface (HPI8)

Three multichannel buffered serial ports (McBSPs)

A hardware timer

A clock generator with a multiple phase-locked loop (PLL)

Enhanced external parallel interface (XIO2)

A DMA controller (DMA)

software-programmable wait-state generator

The software-programmable wait-state generator can extend external bus cycles by up to fourteen CLKOUT cycles, providing a convenient means of interfacing the 'VC5410 with slower external devices. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are shut off; shutting off these paths from the internal clocks allows the device to run with lower power consumption.

The software-programmable wait-state generator is controlled by the 16-bit software wait-state register (SWWSR), which is memory-mapped to address 0028h in data space.

The program and data spaces each consist of two 32K-word blocks; the I/O space consists of one 64K-word block. Each of these blocks has a corresponding 3-bit field in the SWWSR. These fields are shown in Figure 4 and described in Table 2.

The value of a 3-bit field in SWWSR, in conjunction with the software wait-state multiplier (SWSM) bit in the software wait-state control register (SWCR), specifies the number of wait states to be inserted for each access in the corresponding space and address range.

When SWSM = 0, the possible values for the number of wait states are 0, 1, 2, 3, 4, 5, 6, and 7. This is the default configuration.

When SWSM = 1, the possible values for the number of wait states are 0, 2, 4, 6, 8, 10, 12, and 14.

At reset, the SWWSR is set to 7FFFh, and SWSM to 0, configuring seven wait states for all external accesses.

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

15

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

software-programmable wait-state generator (continued)

15

14

12

11

9

8

6

5

3

2

0

SWWSR (0x28)

XPA

I/O

Data

Data

Program

Program

R/W

R/W

R/W

R/W

R/W

R/W

R = Read, W = Write, Reset value = 7FFFh

Figure 4. Software Wait-State Register (SWWSR)

Table 2. Software Wait-State Register Fields

BIT

NAME

RESET

FUNCTION

VALUE

15

XPA

0

Extended program address control bit. XPA selects the address ranges selected by the program fields.

14±12

I/O

1

I/O space. The field value (0±14) corresponds to the number of wait states for I/O space 0000±FFFFh.

11±9

Data

1

Data space. The field value (0±14) corresponds to the number of wait states for data space

8000±FFFFh.

8±6²

Data

1

Data space. The field value (0±14) corresponds to the number of wait states for data space

0000±7FFFh.

Program space. The field value (0±14) corresponds to the number of wait states for:

5±3

Program

1

XPA = 0

xx8000±xxFFFFh

XPA = 1

400000h±7FFFFF

Program space. The field value (0±14) corresponds to the number of wait states for:

2±0

Program

1

XPA = 0

xx0000±xx7FFFh

XPA = 1

000000±3FFFFFh

²Although this field is present to maintain compatibility with previous C5000 family DSPs, there is no external data space on the 'VC5410 in this address range; therefore, the configuration of this bit field has no effect.

The SWSM bit is located in the software wait-state control register (SWCR), a memory-mapped register (MMR) at address 0x2B, bit 0 position (LSB). The bit fields of the SWCR are shown in Figure 5 and are described in Table 3.

	15				1			0
SWCR (0x2B)						Reserved		SWSM
				Figure 5. Software Wait-State Control Register (SWCR)
					Table 3. Software Wait-State Control Register Fields
BIT	NAME			RESET		FUNCTION
				VALUE
15±1	Reserved			±		Reserved
						Software wait-state multiplier bit.
0	SWSM			0		SWSM = 0 Wait states in SWWSR are not multiplied by 2
						SWSM = 1 Wait states in SWWSR are multiplied by 2

16	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

programmable bank-switching

Programmable bank-switching logic allows the 'VC5410 to switch between external memory banks without requiring external wait states for memories that need additional time to turn off. The bank-switching logic automatically inserts one cycle when accesses cross a 32K-word memory-bank boundary inside program or data space.

Bank-switching is defined by the bank-switching control register (BSCR), which is memory-mapped at address 0029h. The bit fields of the BSCR are shown in Figure 6 and are described in Table 4.

15

14

13

12

11

3

2

1

0

BSCR (0x29)

CONSEC

DIVFCT

IACKOFF

Rsvd

HBH

BH

Rsvd

R/W

R/W

R/W

R

R/W

R/W

R

R = Read, W = Write

Figure 6. Bank-Switching Control Register (BSCR)

Table 4. Bank-Switching Control Register Fields

BIT

NAME

RESET

FUNCTION

VALUE

Consecutive bank-switching. Specifies the bank-switching mode.

Bank-switching on 32K bank boundaries only. This bit is cleared if fast access is desired for

CONSEC = 0

15

CONSEC²

1

continuous memory reads (i.e., no starting and trailing cycles between read cycles).

consecutive bank switches on external memory reads. Each read cycle consists of 3 cycles:

CONSEC = 1

starting cycle, read cycle, and trailing cycle.

CLKOUT output divide factor. The CLKOUT output is driven by an on-chip source having a frequency

equal to 1/(DIVFCT+1) of the DSP clock.

13±14

DIVFCT

11

DIVFCT = 00

CLKOUT is not divided.

DIVFCT = 01

CLKOUT is divided by 2 from the DSP clock.

DIVFCT = 10

CLKOUT is divided by 3 from the DSP clock.

DIVFCT = 11

CLKOUT is divided by 4 from the DSP clock (default value following reset).

signal. IACKOFF is set to 1 at reset.

IACK

signal output off. Controls the output of the

IACK

12

IACKOFF

1

IACKOFF = 0

The

IACK

signal output off function is disabled.

IACKOFF = 1

The

IACK

signal output off function is enabled.

11±3

Rsvd

±

Reserved

HPI bus holder. Controls the HPI bus holder. HBH is cleared to 0 at reset.

2

HBH

0

HBH = 0

The bus holder is disabled.

The bus holder is enabled. When not driven, the HPI data bus, HD[7:0] is held in the previous

HBH = 1

logic level.

Bus holder. Controls the bus holder. BH is cleared to 0 at reset.

1

BH

0

BH = 0

The bus holder is disabled.

The bus holder is enabled. When not driven, the data bus, D[15:0] is held in the previous logic

BH = 1

level.

0

Rsvd

±

Reserved

² For additional information, see the ªenhanced external parallel interface (XIO2)º section of this document.

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17

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

programmable bank-switching (continued)

The 'VC5410 has an internal register that holds the MSB of the last address used for a read or write operation in program or data space. In the non-consecutive bank switches (CONSEC = 0), if the MSB of the address used for the current read does not match that contained in this internal register, the MSTRB (memory strobe) signal is not asserted for one CLKOUT cycle. During this extra cycle, the address bus switches to the new address. The contents of the internal register are replaced with the MSB for the read of the current address. If the MSB of the address used for the current read matches the bits in the register, a normal read cycle occurs.

In non-consecutive bank switches (CONSEC = 0), if repeated reads are performed from the same memory bank, no extra cycles are inserted. When a read is performed from a different memory bank, memory conflicts are avoided by inserting an extra cycle. For more information, see the ªenhanced external parallel interface (XIO2)º section of this document.

The bank-switching mechanism automatically inserts one extra cycle in the following cases:

A memory read followed by another memory read from a different memory bank.

A program-memory read followed by a data-memory read.

A data-memory read followed by a program-memory read.

A program-memory read followed by another program-memory read from a different page.

parallel I/O ports

Each device has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The 'VC5410 can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.

enhanced host-port interface (HPI8)

The enhanced host-port interface (HPI8) in the 'VC5410 is an 8-bit parallel port used to interface a host processor to the DSP. Data can be exchanged between the host processor and the DSP throughout the entire on-chip memory via the DMA controller. The extended program memory pages are also accessible by both the host and the DSP. The DSP and the host control the HPI8 activity through the HPI8 control register (HPIC). The host can address memory through the HPI8 address register (HPIA).

Data transfers of 16-bit words occur as two consecutive bytes with a dedicated pin (HBIL) indicating whether the high or low byte is being transmitted. Two pins (controlled by the host), HCNTL0 and HCNTL1, indicate whether the being exchanged is the most significant or least significant byte. Control pins (HCNTL0 and HCNTL1) determine whether the data is directed to the HPIA, the HPIC, or to memory. The DSP can interrupt the host with a dedicated HINT pin that the host can acknowledge and clear.

The 'VC5410 is the first device in the C5000 family in which the HPI8 can address all on-chip memory, including extended memory pages. Extended memory addresses are defined by a 23-bit address. The HPI8 sets the upper 6 bits of the extended memory address by writing a one to the XHPIA bit in HPIC, and then writing address bits A[22:16] into HPIA. The lower 16 bits of the extended memory address are set by writing a zero to XHPIA, followed by writing bits A[15:0] to HPIA. Similar to previous implementations of the HPI, after a write is performed to XHPIA or HPIA, a memory prefetch is initiated. The XHPIA bit is accessible only to the host. XHPIA is uninitialized following reset. The host should always initialize XHPIA prior to the first HPI8 access following a device reset.

The HPI8 interface has two data strobes (HDS1 and HDS2), a read/write strobe (HR/W), and an address strobe (HAS), to enable a glueless interface to a variety of industry-standard host devices. The HPI8 is easily interfaced to hosts with multiplexed address/data bus, separate address and data buses, one data strobe, and a read/write strobe, or two separate strobes for read and write.

18	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

enhanced host-port interface (HPI8) (continued)

All memory accesses on the 'VC5410 are in shared-access mode, meaning both the DSP and the host can access memory. Asynchronous host accesses are resynchronized internally, and in the event that the CPU and the host both request access to the same memory block, the host has access priority. The HRDY pin provides handshaking to the host during memory access.

The HPI8 also provides the capability to access memory during reset and power-down states. During reset, data or application code can be loaded via the HPI8, and the application can be initiated through the HPI option of the bootloader. During IDLE2/3 states, the HPI8 and the other six DMA channels continue to operate, and all pending DMA events complete before the DSP stops the clocks. The HPI8 has higher priority than the other six DMA channels. The HPI8 continues to have access to memory in IDLE2/3 even after the DSP has stopped the internal clocks as long as X2/CLKIN is maintained. The 'VC5410 HPI8 also remains active during emulation stop. The HPI8 can access any on-chip RAM on the device. The HPI8 memory map for the 'VC5410 is shown in Figure 7. The HPI8 determines memory location by address only (program or data space is not relevant).

Address (Hex)

000 0000

Reserved

000 005F

000 0060

Scratch-Pad

RAM

000 007F

000 0080

DARAM

000 1FFF

000 2000

SARAM1

000 7FFF

000 8000

Reserved

001 7FFF

001 8000

SARAM2

001 FFFF

Figure 7. HPI8 Memory Map

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

19

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

multichannel buffered serial ports

The 'VC5410 device provides three high-speed, full-duplex, multichannel buffered serial ports that allow direct interface to other 'C54x/'LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial-port interface found on other '54x devices. Like their predecessors, the McBSPs provide:

Full-duplex communication

Double-buffer data registers, which allow a continuous data stream

Independent framing and clocking for receive and transmit

In addition, the McBSPs have the following capabilities:

Direct interface to:

±T1/E1 framers

±MVIP switching compatible and ST-BUS compliant devices

±IOM-2 compliant devices

±AC97-compliant devices

±IIS-compliant devices

±Serial peripheral interface (SPIt)

Multichannel transmit and receive of up to 128 channels

A wide selection of data sizes, including 8, 12, 16, 20, 24, or 32 bits

-law and A-law companding

Programmable polarity for both frame synchronization and data clocks

Programmable internal clock and frame generation

The McBSPs consist of separate transmit and receive channels that operate independently. The external interface of each McBSP consists of the following pins:

	BCLKX	Transmit reference clock
	BDX	Transmit data
	BFSX	Transmit frame synchronization
	BCLKR	Receive reference clock
	BDR	Receive data
	BFSR	Receive frame synchronization
	BCLKS	External clock reference for the programmable clock generator

The first six pins listed are identical to the previous serial-port interface pins on the C5000 family of DSPs. The BCLKS pin is an additional signal to provide a clock reference to the McBSP programmable clock generator. As a compatibility option, the 'VC5410 is provided in a 144-pin TQFP package (designated PGE) that is pin-compatible with the 'C548/549 devices. BCLKS is not implemented on this package.

On the transmitter, transmit frame synchronization and clocking are indicated by the BFSX and BCLKX pins, respectively. The CPU or DMA can initiate transmission of data by writing to the data transmit register (DXR). Data written to DXR is shifted out on the BDX pin through a transmit shift register (XSR). This structure allows DXR to be loaded with the next word to be sent while the transmission of the current word is in progress.

On the receiver, receive frame synchronization and clocking are indicated by the BFSR and BCLKR pins respectively. The CPU or DMA can read received data from the data receive register (DRR). Data received on the BDR pin is shifted into a receive shift register (RSR) and then buffered in the receive buffer register (RBR). If DRR is empty, the RBR contents are copied into DRR. If not, RBR holds the data until DRR is available. This structure allows storage of the two previous words while the reception of the current word is in progress.

SPI is a trademark of Motorola Incorporated.

20	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

multichannel buffered serial ports (continued)

The CPU and DMA can move data to and from the McBSPs and can synchronize transfers based on McBSP interrupts, event signals, and status flags. The DMA is capable of handling data movement between the McBSPs and memory with no intervention from the CPU.

In addition to the standard serial-port functions, the McBSP provides programmable clock and frame synchronization generation. Among the programmable functions are:

Frame synchronization pulse width

Frame period

Frame synchronization delay

Clock reference (internal vs. external)

Clock division

Clock and frame synchronization polarity

The on-chip companding hardware allows compression and expansion of data in either -law or A-law format. When companding is used, transmit data is encoded according to specified companding law and received data is decoded to 2s complement format.

The McBSP allows the multiple channels to be independently selected for the transmitter and receiver. When the multiple channels are selected, each frame represents a time-division multiplexed (TDM) data stream. In using TDM data streams, the CPU may only need to process a few of them. Thus, to save memory and bus bandwidth, multichannel selection allows independent enabling of particular channels for transmission and reception. Up to 32 channels in a bit stream of up to 128 channels can be enabled.

The clock-stop mode (CLKSTP) in the McBSP provides compatibility with the serial peripheral interface (SPI) protocol. Clock-stop mode works with only single-phase frames and one word per frame. The word sizes supported by the McBSP are programmable for 8-, 12-, 16-, 20-, 24-, or 32-bit operation. When the McBSP is configured to operate in SPI mode, both the transmitter and the receiver operate together as a master or as a slave.

The McBSP is fully static and operates at arbitrarily low clock frequencies. The maximum frequency is CPU clock frequency divided by 2.

hardware timer

The 'VC5410 device features a 16-bit timing circuit with a 4-bit prescaler. The timer counter is decremented by one every CPU clock cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific status bits.

clock generator

The clock generator provides clocks to the 'VC5410 device, and consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock input is then divided by two (DIV mode) to generate clocks for the 'VC5410 device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the 'VC5410 device.

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

21

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

clock generator (continued)

This clock generator allows system designers to select the clock source. The sources that drive the clock generator are:

A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of the 'VC5410 to enable the internal oscillator.

An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left unconnected.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved.Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:

PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios.

DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Note that upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 ± CLKMD3 pins. The CLKMD pin configured clock options are shown in Table 5.

Table 5. CLKMD Pin Configured Clock Options

	CLKMD1	CLKMD2	CLKMD3	CLKMD REGISTER	CLOCK MODE
				RESET VALUE
	0	0	0	0000h	Divide-by-2, with external source
	0	0	1	1000h	Divide-by-2, with external source
	0	1	0	2000h	Divide-by-2, with external source
	0	1	1	±	Stop mode
	1	0	0	4000h	Divide-by-2, internal oscillator enabled
	1	0	1	0007h	PLLx1 with external source
	1	1	0	6000h	Divide-by-2, with external source
	1	1	1	7000h	Reserved

enhanced external parallel interface (XIO2)

The 'VC5410 external interface has been redesigned to include several improvements, including: simplification of the bus sequence, more immunity to bus contention when transitioning between read and write operation, the ability for external memory access to the DMA controller, and optimization of the power-down modes.

The bus sequence on the 'VC5410 still maintains all of the same interface signals as on previous '54x devices, but the signal sequence has been simplified. Most external accesses now require 3 cycles composed of a leading cycle, an active (read or write) cycle, and a trailing cycle. The leading and trailing cycles provide additional immunity against bus contention when switching between read operations and write operations. To maintain high-speed read access, a consecutive read mode that performs single-cycle reads as on previous '54x devices is available.

22	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

enhanced external parallel interface (XIO2) (continued)

Figure 8 shows the bus sequence for three cases: all I/O reads, memory reads in nonconsecutive mode, or single memory reads in consecutive mode. The accesses shown in Figure 8 always require 3 CLKOUT cycles to complete.

CLKOUT

A[22:0]

D[15:0]

READ

R/W

MSTRB or IOSTRB

PS/DS/IS

Leading

Cycle

Read

Cycle

Trailing

Cycle

Figure 8. Nonconsecutive Memory Read and I/O Read Bus Sequence

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

23

TMS320VC5410

FIXED POINT DIGITAL SIGNAL PROCESSOR

SPRS075D ± OCTOBER 1998 ± REVISED MAY 2000

enhanced external parallel interface (XIO2) (continued)

Figure 9 shows the bus sequence for repeated memory reads in consecutive mode. The accesses shown in Figure 9 require (2+n) CLKOUT cycles to complete, where n is the number of consecutive reads performed.

CLKOUT

A[22:0]

D[15:0]

READ

READ

READ

R/W

MSTRB

PS/DS

Leading

Cycle

Read

Cycle

Read

Cycle

Read

Cycle

Trailing

Cycle

Figure 9. Consecutive Memory Read Bus Sequence (n = 3 reads)

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