Texas Instruments TLV5636ID, TLV5636CDR, TLV5636CDGKR, TLV5636CDGK, TLV5636CD Datasheet

	TLV5636
	2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG
	CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
	SLAS223 ± JUNE 1999
features	D OR DGK PACKAGE
	(TOP VIEW)

D D D

D

D D

12-Bit Voltage Output DAC	DIN						VDD
Programmable Internal Reference					1	8
Programmable Settling Time:	SCLK				2	7	OUT
1 μs in Fast Mode,		CS			3	6	REF
		FS			4	5	AGND
3.5 μs in Slow Mode
Compatible With TMS320 and SPI Serial
Ports
Differential Nonlinearity . . . <0.5 LSB Typ
Monotonic Over Temperature

applications

DDigital Servo Control Loops

DDigital Offset and Gain Adjustment

DIndustrial Process Control

DMachine and Motion Control Devices

DMass Storage Devices

description

The TLV5636 is a 12-bit voltage output DAC with a flexible 4-wire serial interface. The serial interface allows glueless interface to TMS320 and SPI , QSPI , and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The programmable settling time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, the TLV5636 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC and 8-pin MSOP package to reduce board space in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

		PACKAGE
TA
	SOIC		MSOP
	(D)		(DGK)
0°C to 70°C	TLV5636CD		TLV5636CDGK
± 40°C to 85°C	TLV5636ID		TLV5636IDGK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1999, Texas Instruments Incorporated

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1

TLV5636

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS223 ± JUNE 1999

functional block diagram

		REF
		PGA With
		Output Enable
		Voltage
		Bandgap
		Power
	Power-On	and Speed
	Reset	Control
		2
		2
		2-Bit
		Control
DIN		Latch
	Serial
SCLK	Interface
CS	and	12	12
	Control	12-Bit	x2	OUT
		DAC
FS		Latch
		Terminal Functions

		TERMINAL		I/O/P	DESCRIPTION
	NAME		NO.
	AGND		5	P	Ground
			3	I	Chip select. Digital input active low, used to enable/disable inputs
	CS
	DIN		1	I	Digital serial data input
	FS		4	I	Frame sync input
	OUT		7	O	DAC A analog voltage output
	REF		6	I/O	Analog reference voltage input/output
	SCLK		2	I	Digital serial clock input
	VDD		8	P	Positive power supply

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TLV5636 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS223 ± JUNE 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . 7	V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	± 0.3 V to VDD + 0.3	V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	± 0.3 V to VDD + 0.3	V
Operating free-air temperature range, TA: TLV5636C . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 0°C to 70°C
TLV5636I . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

			MIN	NOM	MAX	UNIT
	Supply voltage, VDD	VDD = 5 V	4.5	5	5.5	V
		VDD = 3 V	2.7	3	3.3	V
	Power on Reset, POR		0.55		2	V
	High-level digital input voltage, VIH	VDD = 2.7 V to 5.5 V	2			V
	Low-level digital input voltage, VIL	VDD = 2.7 V to 5.5 V			0.8	V
	Reference voltage, Vref to REF terminal	VDD = 5 V (see Note 1)	AGND	2.048	VDD ±1.5	V
	Reference voltage, Vref to REF terminal	VDD = 3 V (see Note 1)	AGND	1.024	VDD ± 1.5	V
	Load resistance, RL		2			kΩ
	Load capacitance, CL				100	pF
	Clock frequency, fCLK				20	MHz
	Operating free-air temperature, TA	TLV5636C	0		70	°C
		TLV5636I	±40		85

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD±0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used.

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3

TLV5636

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS223 ± JUNE 1999

electrical characteristics over recommended operating conditions (unless otherwise noted)

power supply

	PARAMETER		TEST CONDITIONS				MIN	TYP	MAX	UNIT
			No load,			Fast		2.3	3.3
IDD	Power supply current		All inputs = AGND or VDD,							mA
						Slow		1.5	1.9
			DAC latch = 0x800
	Power-down supply current		See Figure 8					0.01	10	mA
PSRR	Power supply rejection ratio		Zero scale,	See Note 2				±65		dB
			Full scale,	See Note 3				±65
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
	PSRR = 20 log [(EZS(VDDmax) ± EZS(VDDmin))/VDDmax]
	3. Power supply rejection ratio at full scale is measured by varying VDD and is given by:
	PSRR = 20 log [(EG(VDDmax) ± EG(VDDmin))/VDDmax]
static DAC specifications
	PARAMETER		TEST CONDITIONS				MIN	TYP	MAX	UNIT
	Resolution						12			bits
INL	Integral nonlinearity, end point adjusted	See Note 4						± 2	± 4	LSB
DNL	Differential nonlinearity	See Note 5						± 0.5	± 1	LSB
EZS	Zero-scale error (offset error at zero scale)	See Note 6							±20	mV
EZS TC	Zero-scale-error temperature coefficient	See Note 7						10		ppm/°C
EG	Gain error	See Note 8							± 0.6	% full
										scale V
EG TC	Gain error temperature coefficient	See Note 9						10		ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5.The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

6.Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7.Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) ± EZS (Tmin)]/Vref × 106/(Tmax ± Tmin).

8.Gain error is the deviation from the ideal output (2Vref ± 1 LSB) with an output load of 10 kW excluding the effects of the zero-error.

9.Gain temperature coefficient is given by: EG TC = [EG(Tmax) ± EG (Tmin)]/Vref × 106/(Tmax ± Tmin).

output specifications

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VO	Output voltage	RL = 10 kW	0		VDD±0.4	V
	Output load regulation accuracy	VO = 4.096 V, 2.048 V RL = 2 kW			± 0.25	% full
						scale V

reference pin configured as output (REF)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Vref(OUTL)	Low reference voltage		1.003	1.024	1.045	V
Vref(OUTH)	High reference voltage	VDD > 4.75 V	2.027	2.048	2.069	V
Iref(source)	Output source current				1	mA
Iref(sink)	Output sink current		±1			mA
	Load capacitance				100	pF
PSRR	Power supply rejection ratio			±65		dB

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TLV5636 2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS223 ± JUNE 1999

electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued)

reference pin configured as input (REF)

	PARAMETER	TEST CONDITIONS		MIN TYP	MAX	UNIT
VI	Input voltage			0	VDD±1.5	V
RI	Input resistance			10		MΩ
CI	Input capacitance			5		pF
	Reference input bandwidth	REF = 0.2 Vpp + 1.024 V dc	Fast	1.3		MHz
			Slow	525		kHz
	Reference feedthrough	REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)		± 80		dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
IIH	High-level digital input current	VI = VDD			1	μA
IIL	Low-level digital input current	VI = 0 V	±1			μA
Ci	Input capacitance			8		pF

analog output dynamic performance

	PARAMETER	TEST CONDITIONS			MIN	TYP	MAX	UNIT
ts(FS)	Output settling time, full scale	RL = 10 kΩ,	CL = 100 pF,	Fast		1	3	μs
		See Note 11		Slow		3.5	7
ts(CC)	Output settling time, code to code	RL = 10 kΩ,	CL = 100 pF,	Fast		0.5	1.5	μs
		See Note 12		Slow		1	2
SR	Slew rate	RL = 10 kΩ,	CL = 100 pF,	Fast		8		V/μs
				Slow		1.5
		See Note 13
	Glitch energy	DIN = 0 to 1,	fCLK = 100 kHz,			5		nV±S
		CS = VDD
SNR	Signal-to-noise ratio				71	75
S/(N+D)	Signal-to-noise + distortion	fs = 480 kSPS,	fout = 1 kHz,		59	66		dB
THD	Total harmonic distortion	RL = 10 kΩ,	CL = 100 pF			±67	±59
	Spurious free dynamic range				59	69

NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDFand 0xFDF to 0x020 respectively. Not tested, assured by design.

12.Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design.

13.Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

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5

TLV5636

2.7 V TO 5.5 V LOW POWER 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS223 ± JUNE 1999

digital input timing requirements

							MIN NOM MAX	UNIT
	tsu(CS±FS)	Setup time,		low before FS falling edge			10	ns
			CS
	tsu(FS-CK)	Setup time, FS low before first negative SCLK edge					8	ns
	tsu(C16-FS)	Setup time, 16th negative SCLK edge after FS low on which bit D0 is sampled before rising					10	ns
		edge of FS
		Setup time, 16th positive SCLK edge (first positive after D0 is sampled) before				rising
					CS
	t	edge. If FS is used instead of 16th positive edge to update DAC, then setup time between					10	ns
	su(C16-CS)	FS rising edge and CS rising edge.
	twH	SCLK pulse duration high					25	ns
	twL	SCLK pulse duration low					25	ns
	tsu(D)	Setup time, data ready before SCLK falling edge					8	ns
	tH(D)	Hold time, data held valid after SCLK falling edge					5	ns
	twH(FS)	FS pulse duration high					25	ns

PARAMETER MEASUREMENT INFORMATION

				twL	twH
SCLK	X	1		2	3	4	5	15	16	X
		tsu(D) th(D)
DIN	X		D15	D14	D13	D12		D1	D0	X
										tsu(C16-CS)
tsu(CS-FS)
CS
	twH(FS)			tsu(FS-CK)					tsu(C16-FS)

FS

Figure 1. Timing Diagram

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