|
|
|
|
|
TP3054B, TP3057B, TP13054B, TP13057B |
|||||||||
|
|
|
|
|
MONOLITHIC SERIAL INTERFACE |
|||||||||
|
|
|
|
|
COMBINED PCM CODEC AND FILTER |
|||||||||
|
|
|
|
|
SCTS042A ± MAY 1990 ± REVISED JULY 1996 |
|||||||||
|
|
|
|
|
|
|
|
|
|
|||||
D Complete PCM Codec and Filtering |
|
D |
μ-Law ± TP3054B and TP13054B |
|||||||||||
Systems Includes: |
|
|
D |
A-Law ± TP3057B and TP13057B |
||||||||||
± Transmit High-Pass and Low-Pass |
|
D |
± 5-V Operation |
|
|
|
|
|
|
|
||||
|
Filtering |
|
|
|
|
|
|
|
|
|
||||
|
|
|
D Low Operating Power . . . 50 mW Typ |
|||||||||||
± |
Receive Low-Pass Filter With (sin x)/x |
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|||||
|
Correction |
|
|
D |
Power-Down Standby Mode . . . 3 mW Typ |
|||||||||
± Active RC Noise Filters |
|
D |
Automatic Power Down |
|
|
|
||||||||
± μ-Law or A-Law Compatible Coder and |
D TTLor CMOS-Compatible Digital Interface |
|||||||||||||
|
Decoder |
|
|
|||||||||||
|
|
|
D Maximizes Line Interface Card Circuit |
|||||||||||
± |
Internal Precision Voltage Reference |
|
||||||||||||
|
|
Density |
|
|
|
|
|
|
|
|||||
± |
Serial I/O Interface |
|
|
|
|
|
|
|
|
|
|
|||
|
|
|
Improved Versions of National |
|||||||||||
± Internal Autozero Circuitry |
|
D |
||||||||||||
|
|
|
|
|
Semiconductor TP3054, TP3057, TP3054-X, |
|||||||||
|
|
|
|
|
TP3057-X |
|
|
|
|
|
|
|
||
description |
|
|
|
DW OR N PACKAGE |
||||||||||
|
|
|
|
|
||||||||||
The TP3054B, TP3057B, TP13054B, and |
|
|
|
(TOP VIEW) |
|
|
|
|||||||
TP13057B are comprised of a single-chip PCM |
|
|
|
|
|
|
|
|
|
|
||||
codec (pulse-code-modulated encoder and de- |
|
VBB |
|
1 |
16 |
|
|
VFXI+ |
||||||
|
|
|
|
|||||||||||
coder) and PCM line filter. These devices provide |
|
|
|
|
|
|
VFXI± |
|||||||
|
ANLG GND |
|
2 |
15 |
|
|
||||||||
all the functions required to interface a full-duplex |
|
VFRO |
|
3 |
14 |
|
|
GSX |
||||||
|
|
|
|
|||||||||||
(2-wire) voice telephone |
circuit with a |
TDM |
|
VCC |
|
4 |
13 |
|
|
TSX |
|
|||
|
|
|
|
|||||||||||
(time-division-multiplexed) |
system. These |
de- |
|
FSR |
|
5 |
12 |
|
|
FSX |
||||
|
|
|
|
|||||||||||
vices are pin-for-pin compatible with the National |
|
|
|
|
||||||||||
|
DR |
|
6 |
11 |
|
|
DX |
|||||||
|
|
|
|
|||||||||||
Semiconductor TP3054B and TP3057B, respec- |
|
|
|
|
||||||||||
|
BCLKR/CLKSEL |
|
7 |
10 |
|
|
BCLKX |
|||||||
|
|
|
|
|||||||||||
tively. Primary applications include: |
|
|
|
|
|
|||||||||
|
|
MCLKR/PDN |
|
8 |
9 |
|
|
MCLKX |
||||||
|
|
|
|
|
||||||||||
|
• Line interface for digital transmission and |
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
||||
|
switching of T1 carrier, PABX, and central |
|
|
|
|
|
|
|
|
|
|
|||
|
office telephone systems |
|
|
|
|
|
|
|
|
|
|
|
||
|
• Subscriber line concentrators |
|
|
|
|
|
|
|
|
|
|
|
||
|
• Digital-encryption systems |
|
|
|
|
|
|
|
|
|
|
|
||
|
• Digital voice-band data-storage systems |
|
|
|
|
|
|
|
|
|
|
|||
|
• Digital signal processing |
|
|
|
|
|
|
|
|
|
|
|
These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be used at the analog termination of a PCM line or trunk. The devices require two transmit and receive master clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive frame-sync pulses. The TP3054B, TP3057B, TP13054B, and TP13057B provide the band-pass filtering of the analog signals prior to encoding and after decoding of voice and call progress tones. The TP3054B and TP13054B contain patented circuitry to achieve low transmit channel idle noise and are not recommended for applications in which the composite signals on the transmit side are below ±55 dBm0.
The TP3054B and TP3057B are characterized for operation from 0°C to 70°C. The TP13054B and TP13057B are characterized for operation from ±40°C to 85°C.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the CMOS gates.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A ± MAY 1990 ± REVISED JULY 1996
functional block diagram
14
GSX
|
R2 |
Autozero |
|
Logic |
|
Analog |
|
|
|
|
|
Input |
|
|
15 |
R1 |
|
|
|
VFXI ± |
± |
RC |
Switched- |
S/H |
VFXI + 16 |
|
Active Filter |
Capacitor |
|
|
DAC |
|||
+ |
Band-Pass Filter |
|
|
|
|
Voltage |
|
|
|
|
|
|
A/D |
|
|
|
Transmit |
|
|
|
|
|
|
|
Reference |
|
|
|
|
|
Control |
|
|
|
Regulator |
11 |
DX |
||
|
|
|
|
|
|
|
|
|
|
Logic |
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
Comparator |
|
|
|
|
|
|
|
OE |
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3 |
|
|
|
RC Active |
|
Switched- |
|
|
|
S/H |
|
|
|
Receive |
|
|
||
VFRO |
|
|
|
|
Capacitor |
|
|
|
|
|
|
6 |
|
|||||
|
|
|
Filter |
|
|
|
|
DAC |
|
|
|
Regulator |
DR |
|||||
|
|
|
|
|
Low-Pass Filter |
|
|
|
|
|
|
|||||||
Power |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLK |
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
Amplifier |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
13 |
|
|
|
|
|
|
|
|
|
|
|
Timing and Control |
|
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TSX |
|||
5 V |
± 5 V |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
9 |
8 |
|
|
10 |
7 |
5 |
12 |
|
|
|
|||
4 |
1 |
2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VCC |
VBB |
ANLG GND |
|
MCLKX |
MCLKR/ |
BCLKX |
BCLKR/ |
|
FSR FSX |
|
|
|||||||
|
|
|
|
PDN |
|
CLKSEL |
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A ± MAY 1990 ± REVISED JULY 1996
|
|
|
|
Terminal Functions |
|
|
|
|
|
|
|
TERMINAL |
|
DESCRIPTION |
|
|
NAME |
NO. |
|
|
|
|
||
|
|
|
|
|
|
ANLG GND |
2 |
Analog ground. All signals are referenced to ANLG GND. |
|
|
|
|
|
|
|
BCLKR/CLKSEL |
7 |
The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately, |
|
|
|
|
|
BCLKR/CLKSEL can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for the master clock in |
|
|
|
|
the synchronous mode. BCLKX is used for both transmit and receive directions (see Table 1). |
|
|
|
|
|
|
BCLKX |
10 |
The bit clock that shifts out the PCM data on DX. BCLKX can vary from 64 kHz to 2.048 MHz, but must be synchronous |
|
|
|
|
|
with MCLKX. |
|
|
|
|
|
|
DR |
6 |
Receive data input. PCM data is shifted into DR following the FSR leading edge. |
|
|
|
|
|
|
|
DX |
11 |
The 3-state PCM data output that in enabled by FSX |
|
|
|
|
|
|
|
FSR |
5 |
Receive frame-sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see |
|
|
|
|
|
Figures 1 and 2 for timing details). |
|
|
|
|
|
|
FSX |
12 |
Transmit frame-sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see |
|
|
|
|
|
Figures 1 and 2 for timing details). |
|
|
|
|
|
|
GSX |
14 |
Analog output of the transmit input amplifier. GSX is used to externally set gain. |
|
|
|
|
|
|
|
MCLKR/PDN |
8 |
Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should |
|
|
|
|
|
be synchronous with MCLKX for best performance. When MCLKR is connected continuously low, MCLKX is selected |
|
|
|
|
for all internal timing. When MCLKR is connected continuously high, the device is powered down. |
|
|
|
|
|
|
MCLKX |
9 |
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR. |
|
|
|
|
|
|
|
|
|
13 |
Open-drain output that pulses low during the encoder time slot |
|
TSX |
|
||
|
|
|
|
|
|
VBB |
1 |
Negative power supply pin. VBB = ± 5 V ± 5% |
|
|
VCC |
4 |
Positive power supply pin. VCC = 5 V ± 5% |
|
|
VFRO |
3 |
Analog output of the receive filter |
|
|
|
|
|
|
|
VFXI + |
16 |
Noninverting input of the transmit input amplifier |
|
|
|
|
|
|
|
VFXI ± |
15 |
Inverting input of the transmit input amplifier |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A ± MAY 1990 ± REVISED JULY 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . |
. . . . . . . . . . . 7 V |
Supply voltage, VBB (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . |
. . . . . . . . . ±7 V |
Voltage range at any analog input or output . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . VCC +0.3 V to VBB ±0.3 V |
|
Voltage range at any digital input or output . . . . . . . . . . . . . . . . . . . . . . . . . . |
VCC +0.3 V to ANLG GND ±0.3 V |
|
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . See Dissipation Rating Table |
|
Operating free-air temperature range, TA: TP3054B, TP3057B . . . . . . . . |
. . . . . . . . . . . . . . . . |
. . 0°C to 70°C |
TP13054B, TP13057B . . . . . . |
. . . . . . . . . . . . . . . . |
±40°C to 85°C |
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . |
±65°C to 150°C |
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package . . . . . . . . |
. . . . . . . 260°C |
²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
|
|
DISSIPATION RATING TABLE |
|
||
PACKAGE |
TA ≤ 25°C |
DERATING FACTOR |
TA = 70°C |
TA = 85°C |
|
POWER RATING |
ABOVE TA = 25°C |
POWER RATING |
POWER RATING |
||
|
|||||
DW |
1025 mW |
8.2 mW/°C |
656 mW |
533 mW |
|
N |
1150 mW |
9.2 mW/°C |
736 mW |
598 mW |
recommended operating conditions (see Note 2)
|
|
MIN |
NOM |
MAX |
UNIT |
|
|
|
|
|
|
Supply voltage, VCC |
|
4.75 |
5 |
5.25 |
V |
Supply voltage, VBB |
|
± 4.75 |
± 5 |
± 5.25 |
V |
High-level input voltage, VIH |
|
2.2 |
|
|
V |
Low-level input voltage, VIL |
|
|
|
0.6 |
V |
Common-mode input voltage range, VICR³ |
|
|
|
± 2.5 |
V |
Load resistance, GSX, RL |
|
10 |
|
|
kΩ |
Load capacitance, GSX, CL |
|
|
|
50 |
pF |
Operating free-air temperature, TA |
TP3054B, TP3057B |
0 |
|
70 |
°C |
|
|
|
|
||
TP13054B, TP13057B |
± 40 |
|
85 |
||
|
|
|
|||
|
|
|
|
|
|
³ Measured with CMRR > 60 dB.
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device power-up sequence paragraphs later in this document should be followed.
4 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A ± MAY 1990 ± REVISED JULY 1996
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
supply current
|
PARAMETER |
|
TEST CONDITIONS |
TP305xB |
|
TP1305xB |
|
UNIT |
|
|
|
|
|
|
|
||||
|
|
MIN TYP |
MAX |
MIN TYP |
MAX |
||||
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
ICC |
Supply current from VCC |
Power down |
No load |
0.5 |
1 |
0.5 |
1.2 |
mA |
|
|
|
|
|
|
|||||
Active |
6 |
9 |
6 |
10 |
|||||
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
IBB |
Supply current from VBB |
Power down |
No load |
0.5 |
1 |
0.5 |
1.2 |
mA |
|
|
|
|
|
|
|||||
Active |
6 |
9 |
6 |
10 |
|||||
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
electrical characteristics at VCC = 5 V ± 5%, VBB = ±5 V ± 5%, GND at 0 V, TA = 25°C (unless otherwise noted)
digital interface
|
PARAMETER |
|
|
|
TEST CONDITIONS |
MIN MAX |
UNIT |
|
|
|
|
|
|
|
|
|
|
VOH |
High-level output voltage |
|
DX |
IH = ± 3.2 mA |
|
2.4 |
V |
|
VOL |
Low-level output voltage |
|
DX |
IL = 3.2 mA |
|
0.4 |
V |
|
|
|
|
|
|
|
|||
|
TSX |
IL = 3.2 mA, |
Drain open |
0.4 |
||||
|
|
|
|
|||||
IIH |
High-level input current |
|
|
|
VI = VIH to VCC |
|
± 10 |
μA |
IIL |
Low-level input current |
|
All digital inputs |
VI = GND to VIL |
|
± 10 |
μA |
|
VOL |
Output current in high-impedance state |
|
DX |
VO = GND to VCC |
|
± 10 |
μA |
analog interface with transmit amplifier input
|
|
PARAMETER |
TEST CONDITIONS |
|
MIN |
TYP² |
MAX |
UNIT |
|||||||
II |
Input current |
|
|
|
|
|
VFXI + or VFXI ± |
VI = ± 2.5 V to 2.5 V |
|
|
|
|
± 200 |
nA |
|
ri |
Input resistance |
|
|
|
|
|
VFXI + or VFXI ± |
VI = ± 2.5 V to 2.5 V |
|
10 |
|
|
MΩ |
||
ro |
Output resistance |
|
|
|
|
|
|
Closed loop, |
Unity gain |
|
|
1 |
3 |
Ω |
|
|
Output dynamic range |
|
|
|
GSX |
RL ≥ 10 kΩ |
|
|
|
|
± 2.8 |
V |
|||
AV |
Open-loop voltage amplification |
|
|
VFXI + to GSX |
|
|
5000 |
|
|
|
|||||
BI |
Unity-gain bandwidth |
|
|
|
GSX |
|
|
1 |
2 |
|
MHz |
||||
VIO |
Input offset voltage |
|
|
|
|
VFXI + or VFXI ± |
|
|
|
|
|
± 20 |
mV |
||
CMRR |
Common-mode rejection ratio |
|
|
|
|
|
|
60 |
|
|
dB |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
KSVR |
Supply-voltage rejection ratio |
|
|
|
|
|
|
60 |
|
|
dB |
||||
² All typical values are at V |
CC |
= 5 V, V |
BB |
= ± 5 V, and T = 25°C. |
|
|
|
|
|
|
|
||||
|
|
|
|
|
A |
|
|
|
|
|
|
|
|||
analog interface with receive filter |
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
|
PARAMETER |
|
|
|
|
TEST CONDITIONS |
|
MIN |
TYP² |
MAX |
UNIT |
|||
Output resistance |
|
|
|
|
VFRO |
|
|
|
|
|
1 |
3 |
Ω |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Load resistance |
|
|
|
|
|
|
|
VFRO = ± 2.5 V |
|
600 |
|
|
Ω |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Load capacitance |
|
|
|
|
VFRO to GND |
|
|
|
|
|
|
500 |
pF |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
Output dc offset voltage |
|
|
|
|
VFRO to GND |
|
|
|
|
|
|
± 200 |
mV |
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
² All typical values are at V |
CC |
= 5 V, V |
BB |
= ± 5 V, |
and T = 25°C. |
|
|
|
|
|
|
|
|
||
|
|
|
|
|
A |
|
|
|
|
|
|
|
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
5 |
TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A ± MAY 1990 ± REVISED JULY 1996
operating characteristics, over operating free-air temperature range, VCC = 5 V ± 5%,
VBB = ±5 V ± 5%, GND at 0 V, VI = 1.2276 V, f = 1.02 kHz, transmit input amplifier connected for unity gain, noninverting (unless otherwise noted)
timing requirements
|
PARAMETER |
|
|
|
|
TEST CONDITIONS |
MIN TYP² |
MAX |
UNIT |
||||
|
|
|
|
|
|
|
|
|
MCLKX and |
Depends on the device used and |
1.536 |
|
|
fclock(M) |
Frequency of master clock |
|
|
|
1.544 |
|
MHz |
||||||
|
|
|
MCLKR |
BCLKX/CLKSEL |
|
||||||||
|
|
|
|
|
|
|
|
|
2.048 |
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
fclock(B) |
Frequency of bit clock, transmit |
|
BCLKX |
|
64 |
2.048 |
kHz |
||||||
tw1 |
Pulse duration, MCLKX and MCLKR high |
|
|
160 |
|
ns |
|||||||
tw2 |
Pulse duration, MCLKX and MCLKR low |
|
|
160 |
|
ns |
|||||||
tr1 |
Rise time of master clock |
|
|
|
|
|
MCLKX and |
Measured from 20% to 80% |
|
50 |
ns |
||
|
|
|
|
|
MCLKR |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
tf1 |
Fall time of master clock |
|
|
|
|
|
MCLKX and |
Measured from 20% to 80% |
|
50 |
ns |
||
|
|
|
|
|
MCLKR |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
tr2 |
Rise time of bit clock, transmit |
|
BCLKX |
Measured from 20% to 80% |
|
50 |
ns |
||||||
tf2 |
Fall time of bit clock, transmit |
|
|
|
BCLKX |
Measured from 20% to 80% |
|
50 |
ns |
||||
tsu1 |
Setup time, BCLKX high (and FSX in long-frame sync |
First bit clock after the leading edge |
100 |
|
ns |
||||||||
mode) before MCLKX↓ |
|
|
|
|
|
|
of FSX |
|
|||||
tw3 |
Pulse duration, BCLKX and BCLKR high |
|
VIH = 2.2 V |
160 |
|
ns |
|||||||
tw4 |
Pulse duration, BCLKX and BCLKR low |
|
VIL = 0.6 V |
160 |
|
ns |
|||||||
th1 |
Hold time, frame sync low after bit clock low |
|
0 |
|
ns |
||||||||
(long frame only) |
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|||||
th2 |
Hold time, BCLKX high after frame sync↑ |
|
|
0 |
|
ns |
|||||||
(short frame only) |
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
||||||
tsu2 |
Setup time, frame sync high before bit clock↓ |
|
80 |
|
ns |
||||||||
(long frame only) |
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|||||
t |
Delay time, BCLKX high to data valid |
|
Load = 150 pF plus 2 LSTTL loads³ |
0 |
140 |
ns |
|||||||
d1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
t |
Delay time, BCLKX high to |
TSX |
low |
|
Load = 150 pF plus 2 LSTTL loads³ |
|
140 |
ns |
|||||
d2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
td3 |
Delay time, BCLKX (or 8 clock FSX in long frame |
|
50 |
165 |
ns |
||||||||
only) low to data output disabled |
|
|
|||||||||||
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
||||||||
td4 |
Delay time, FSX or BCLKX high to data valid |
CL = 0 pF to 150 pF |
20 |
165 |
ns |
||||||||
(long frame only) |
|
|
|
|
|
|
|
||||||
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|||||||
tsu3 |
Setup time, DR valid before BCLKR↓ |
|
|
50 |
|
ns |
|||||||
th3 |
Hold time, DR valid after BCLKR or BCLKX↓ |
|
50 |
|
ns |
||||||||
tsu4 |
Setup time, FSR or FSX high before BCLKR or |
Short-frame sync pulse (1 or 2 bit |
50 |
|
ns |
||||||||
BCLKR↓ |
|
|
|
|
|
|
|
|
clock periods long) (see Note 3) |
|
|||
t |
Hold time, FSX or FSR high after BCLKX or BCLKR↓ |
Short-frame sync pulse (1 or 2 bit |
100 |
|
ns |
||||||||
h4 |
|
|
|
|
|
|
|
|
|
clock periods long) (see Note 3) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
th5 |
Hold time, frame sync high after bit clock↓ |
Long-frame sync pulse (from 3 to |
100 |
|
ns |
||||||||
8 bit clock periods long) |
|
||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
tw5 |
Minimum pulse duration of the frame sync pulse |
64 kbps operating mode |
160 |
|
ns |
||||||||
(low level) |
|
|
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
² All typical values are at V |
CC |
= 5 V, V |
BB |
= ± 5 V, and T = 25°C. |
|
|
|
|
|||||
|
|
|
|
|
|
A |
|
|
|
|
|||
³ Nominal input value for an LSTTL lead is 18 kW. |
|
|
|
|
|
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.
6 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |