Texas Instruments TMS27C512-10JE, TMS27PC512-25FML, TMS27PC512-25FME, TMS27PC512-20FML, TMS27PC512-20FME Datasheet

DOrganization . . . 65536 by 8 Bits

DSingle 5-V Power Supply

DPin Compatible With Existing 512K MOS ROMs, PROMs, and EPROMs

DAll Inputs/Outputs Fully TTL Compatible

DMax Access/Min Cycle Time

VCC ± 10%
'27C/PC512-10	100 ns
'27C/PC512-12	120 ns
'27C/PC512-15	150 ns
'27C/PC512-20	200 ns
'27C/PC512-25	250 ns

DPower Saving CMOS Technology

DVery High-Speed SNAP! Pulse Programming

D3-State Output Buffers

D400-mV Minimum DC Noise Immunity With Standard TTL Loads

DLatchup Immunity of 250 mA on All Input and Output Lines

DLow Power Dissipation ( VCC = 5.25 V )

±Active . . . 158 mW Worst Case

±Standby . . . 1.4 mW Worst Case (CMOS Input Levels)

DTemperature Range Options

D512K EPROM Available With MIL-STD-883C Class B High Reliability Processing (SMJ27C512)

description

The TMS27C512 series are 65536 by 8-bit (524288-bit), ultraviolet (UV) light erasable, electrically programmable read-only memories (EPROMs).

The TMS27PC512 series are 65536 by 8-bit (524288-bit), one-time programmable (OTP) electrically programmable read-only memories (PROMs).

TMS27C512 65536 BY 8-BIT UV ERASABLE TMS27PC512 65536 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G ± NOVEMBER 1985 ± REVISED SEPTEMBER 1997

J PACKAGE ( TOP VIEW )

							A15					1					28				VCC
							A12					2					27				A14
								A7				3					26				A13
								A6				4					25				A8
								A5				5					24				A9
								A4				6					23				A11
								A3				7					22				G			/ VPP
								A2				8					21				A10
								A1				9					20				E
								A0				10					19				DQ7
							DQ0					11					18				DQ6
							DQ1					12					17				DQ5
							DQ2					13					16				DQ4
							GND					14					15				DQ3
										FM PACKAGE
											( TOP VIEW )
								A7		A12			A15		NU		CC					A13
																	V A14
			A6				4			3		2			1		32 31 30											A8
						5																29
			A5			6																28						A9
			A4			7																27						A11
			A3			8																26						NC
			A2
						9																25							G		/ VPP
			A1			10																24						A10
			A0			11																23							E
			NC			12																22						DQ7
			DQ0			13																21						DQ6
						14 15 16									17 18 19							20
								DQ1		DQ2			GND		NU		DQ3 DQ4					DQ5
							PIN NOMENCLATURE
	A0 ± A15							Address Inputs
	E						Chip Enable/Power Down
	DQ0 ± DQ7							Inputs (programming) / Outputs
	G		/ VPP				13-V Programming Power Supply
	GND						Ground
	NC						No Internal Connection
	NU						Make No External Connection
	VCC						5-V Power Supply

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

Copyright 1997, Texas Instruments Incorporated

1

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G ± NOVEMBER 1985 ± REVISED SEPTEMBER 1997

description (continued)

These devices are fabricated using power-saving CMOS technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits without the use of external pullup resistors. Each output can drive one Series 74 TTL circuit without external resistors.

The data outputs are 3-state for connecting multiple devices to a common bus. The TMS27C512 and the TMS27PC512 are pin compatible with 28-pin 512K MOS ROMs, PROMs, and EPROMs.

The TMS27C512 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in mounting hole rows on 15,2-mm (600-mil) centers. The TMS27PC512 OTP PROM is supplied in a 32-lead plastic leaded chip carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).

The TMS27C512 and TMS27PC512 are offered with two choices of temperature ranges of 0°C to 70°C (JL and FML suffix) and ± 40°C to 85°C (JE and FME suffix). See Table 1.

All package styles conform to JEDEC standards.

Table 1. Temperature Range Suffixes

EPROM	SUFFIX FOR OPERATING
AND	FREE-AIR TEMPERATURE RANGES
OTP PROM	0°C TO 70°C	± 40°C TO 85°C
TMS27C512-xxx	JL	JE
TMS27PC512-xxx	FML	FME

These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use in microprocessor-based systems. One other 13-V supply is needed for programming. All programming signals are TTL level. The device is programmed using the SNAP! Pulse programming algorithm. The SNAP! Pulse programming algorithm uses a VPP of 13 V and a VCC of 6.5 V for a nominal programming time of seven seconds. For programming outside the system, existing EPROM programmers can be used. Locations can be programmed singly, in blocks, or at random.

2	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G ± NOVEMBER 1985 ± REVISED SEPTEMBER 1997

operation

The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are TTL level except for VPP during programming (13 V for SNAP! Pulse) and 12 V on A9 for signature mode.

Table 2. Operation Modes

MODE²

FUNCTION

READ

OUTPUT

STANDBY

PROGRAMMING

VERIFY

PROGRAM

SIGNATURE

DISABLE

INHIBIT

MODE

VIL

VIL

VIH

VIL

VIL

VIH

VIL

E

/ VPP

VIL

VIH

X

VPP

VIL

VPP

VIL

G

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

A9

X

X

X

X

X

X

V ³

V

H

³

H

A0

X

X

X

X

X

X

VIL

VIH

CODE

DQ0 ± DQ7

Data Out

Hi-Z

Hi-Z

Data In

Data Out

Hi-Z

MFG

DEVICE

97

85

² X can be VIL or VIH. ³ VH = 12 V ± 0.5 V.

read/output disable

When the outputs of two or more TMS27C512s or TMS27PC512s are connected in parallel on the same bus, the output of any particular device in the circuit can be read with no interference from the competing outputs of the other devices. To read the output of a single device, a low-level signal is applied to the E and G/VPP pins. All other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these pins. Output data is accessed at pins DQ0 through DQ7.

latchup immunity

Latchup immunity on the TMS27C512 and TMS27PC512 is a minimum of 250 mA on all inputs and outputs. This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup without compromising performance or packing density.

power down

Active ICC supply current can be reduced from 30 mA to 500 mA (TTL-level inputs) or 250 mA (CMOS-level

inputs) by applying a high TTL/CMOS signal to the E pin. In this mode all outputs are in the high-impedance state.

erasure (TMS27C512)

Before programming, the TMS27C512 EPROM is erased by exposing the chip through the transparent lid to a high intensity ultraviolet light (wavelength 2537 angstroms). EPROM erasure before programming is necessary to assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. A programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV intensity × exposure time) is 15-W s/cm2. A typical 12-mW/cm2, filterless UV lamp erases the device in 21 minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C512, the window should be covered with an opaque label.

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

3

TMS27C512 65536 BY 8-BIT UV ERASABLE

TMS27PC512 65536 BY 8-BIT

PROGRAMMABLE READ-ONLY MEMORIES

SMLS512G ± NOVEMBER 1985 ± REVISED SEPTEMBER 1997

initializing (TMS27PC512)

The one-time programmable TMS27PC512 PROM is provided with all bits in the logic high state, then logic lows are programmed into the desired locations. Logic lows programmed into a PROM cannot be erased.

SNAP! Pulse programming

The 512K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm illustrated by the flowchart in Figure 1, which programs in a nominal time of seven seconds. Actual programming time varies as a function of the programmer used.

The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (μs) followed by a byte verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-μs pulses per byte are provided before a failure is recognized.

The programming mode is achieved with G/VPP = 13 V, VCC = 6.5 V, and E = VIL. Data is presented in parallel

(eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E is pulsed.

More than one device can be programmed when the devices are connected in parallel. Locations can be programmed in any order. When the SNAP! Pulse programming routine is complete, all bits are verified with VCC = 5 V, G/VPP = VIL, and E = VIL.

program inhibit

Programming can be inhibited by maintaining a high level input on the E pin.

program verify

Programmed bits can be verified when G/VPP and E = VIL.

signature mode

The signature mode provides access to a binary code identifying the manufacturer and type. This mode is activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other addresses must be held low. the signature code for these devices is 9785. A0 selects the manufacturer's code 97 (Hex), and A0 high selects the device code 85, as shown in Table 3.

Table 3. Signature Mode

IDENTIFIER²

PINS

A0

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

HEX

Manufacturer Code

VIL

1

0

0

1

0

1

1

1

97

Device Code

VIH

1

0

0

0

0

1

0

1

85

²

=

= V

, A9 = V

, A1 ± A8 = V , A10 ± A15 = V ,

= V

or V .

E

G

H

PGM

IH

IL

IL

IL

IL

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