Texas Instruments TPS2010D, TPS2012PWLE, TPS2012PWR, TPS2012DR, TPS2012D Datasheet

TPS2010, TPS2011, TPS2012, TPS2013

POWER-DISTRIBUTION

SLVS097A ± DECEMBER 1994 ± REVISED AUGUST 1995

D 95-mΩ Max (5.5-V Input) High-Side MOSFET							D PACKAGE
Switch With Logic Compatible Enable Input								(TOP VIEW)
D Short-Circuit and Thermal Protection	GND										OUT
								1		8
D Typical Short-Circuit Current Limits:
			IN					2		7	OUT
0.4 A, TPS2010; 1.2 A, TPS2011;			IN					3		6	OUT
2 A, TPS2012; 2.6 A, TPS2013
	EN							4		5	OUT
D Electrostatic-Discharge Protection, 12-kV
Output, 6-kV All Other Terminals							PW PACKAGE
D Controlled Rise and Fall Times to Limit									(TOP VIEW)
Current Surges and Minimize EMI	GND										OUT
									1	14
D SOIC-8 Package Pin Compatible With the
			IN								OUT
Popular Littlefoot Series When GND Is									2	13
			IN								OUT
Connected									3	12
			IN						4	11	OUT
D 2.7-V to 5.5-V Operating Range
			IN						5	10	OUT
D 10-µA Maximum Standby Current
			IN						6	9	OUT
D Surface-Mount SOIC-8 and TSSOP-14
											OUT
			EN						7	8
Packages
D ±40°C to 125°C Operating Junction
Temperature Range

description

The TPS201x family of power-distribution switches is intended for applications where heavy capacitive loads and short circuits are likely to be encountered. The high-side switch is a 95-mΩ N-channel MOSFET. Gate drive is provided by an internal driver and charge pump designed to control the power switch rise times and fall times to minimize current surges during switching. The charge pump operates at 100 kHz, requires no external components, and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit threshold or a short circuit is present, the TPS201x limits the output current to a safe level by switching into a constant-current mode. Continuous heavy overloads and short circuits increase power dissipation in the switch and cause the junction temperature to rise. If the junction temperature reaches approximately 180°C, a thermal protection circuit shuts the switch off to prevent damage. Recovery from thermal shutdown is automatic once the device has cooled sufficiently.

The members of the TPS201x family differ only in short-circuit current threshold. The TPS2010 is designed to limit at 0.4-A load; the other members of the family limit at 1.2 A, 2 A, and 2.6 A (see the available options table). The TPS201x family is available in 8-pin small-outline integrated circuit (SOIC) and 14-pin thin shink small-outline (TSSOP) packages and operates over a junction temperature range of ±40°C to 125°C. Versions in the 8-pin SOIC package are drop-in replacements for Siliconix's Littlefoot power PMOS switches, except that GND must be connected.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1995, Texas Instruments Incorporated

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1

TPS2010, TPS2011, TPS2012, TPS2013

POWER-DISTRIBUTION

SLVS097A ± DECEMBER 1994 ± REVISED AUGUST 1995

AVAILABLE OPTIONS

		RECOMMENDED MAXIMUM	TYPICAL SHORT-CIRCUIT	PACKAGED DEVICES		CHIP
	TJ	CONTINUOUS LOAD CURRENT	OUTPUT CURRENT LIMIT AT 25°C	SOIC	TSSOP	FORM
		(A)	(A)	(D)²	(PW)³	(Y)
		0.2	0.4	TPS2010D	TPS2010PWLE	TPS2010Y
	±40°C to 125°C	0.6	1.2	TPS2011D	TPS2011PWLE	TPS2011Y
		1	2	TPS2012D	TPS2012PWLE	TPS2012Y
		1.5	2.6	TPS2013D	TPS2013PWLE	TPS2013Y

² The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2010DR).

³ The PW package is only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TPS2010PWLE).

functional block diagram

	Power Switch
IN	CS ²	OUT

Charge

Pump

EN	Driver
GND	Thermal
	Sense
² Current sense

Current

Limit

Terminal Functions

			TERMINAL
	NAME			NO.		I/O	DESCRIPTION
				D	PW
				4	7	I	Enable input. Logic low turns power switch on.
	EN
	GND			1	1	I	Ground
	IN			2, 3	2 ± 6	I	Input voltage
	OUT			5 ± 8	8 ± 14	O	Power-switch output

detailed description

power switch

The power switch is an N-channel MOSFET with a maximum on-state resistance of 95 mΩ (VI(IN) = 5.5 V), configured as a high-side switch.

charge pump

An internal 100-kHz charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires very little supply current.

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TPS2010, TPS2011, TPS2012, TPS2013

POWER-DISTRIBUTION

SLVS097A ± DECEMBER 1994 ± REVISED AUGUST 1995

detailed description (continued)

driver

The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range instead of the microsecond or nanosecond range for a standard FET.

enable (EN)

A logic high on the EN input turns off the power switch and the bias for the charge pump, driver, and other circuitry to reduce the supply current to less than 10 A. A logic zero input restores bias to the drive and control circuits and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.

current sense

A sense FET monitors the current supplied to the load. The sense FET is a much more efficient way to measure current than conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into its linear region, which switches the output into a constant current mode and simply holds the current constant while varying the voltage on the load.

thermal sense

An internal thermal-sense circuit shuts the power switch off when the junction temperature rises to approximately 180°C. Hysteresis is built into the thermal sense, and after the device has cooled approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed.

TPS201xY chip information

This chip, when properly assembled, displays characteristics similar to the TPS201xC. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with conductive epoxy or a gold-silicon preform.

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TPS2010, TPS2011, TPS2012, TPS2013

POWER-DISTRIBUTION

SLVS097A ± DECEMBER 1994 ± REVISED AUGUST 1995

	BONDING PAD ASSIGNMENTS
(1)	(8)	(7)	GND			(1)		(8)			OUT
						(2)		(7)
				IN							OUT
							TPS201xY
						(3)		(6)
				IN							OUT
						(4)		(5)
											OUT
(2)			EN

81

(3)
					CHIP THICKNESS: 15 MILS TYPICAL
					BONDING PADS: 4 × 4 MILS MINIMUM
					TJmax = 150°C
					TOLERANCES ARE ± 10%
(4)	(5)		(6)		ALL DIMENSIONS ARE IN MILS
	72

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Input voltage range, VI(IN) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . . . . ±0.3 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . ±0.3 V to VI(IN) +0.3 V
Input voltage range, VI at	EN	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . ±0.3 V to 7 V
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . ±40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			. . . . . . . . . . ±65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . .			. . . . . . . . . . . . . . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

	PACKAGE	TA ≤ 25°C	DERATING FACTOR	TA = 70°C	TA = 125°C
		POWER RATING	ABOVE TA = 25°C	POWER RATING	POWER RATING
	D	725 mW	5.8 mW/°C	464 mW	145 mW
	PW	700 mW	5.6 mW/°C	448 mW	140 mW

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TPS2010, TPS2011, TPS2012, TPS2013

POWER-DISTRIBUTION

SLVS097A ± DECEMBER 1994 ± REVISED AUGUST 1995

recommended operating conditions

					MIN	MAX	UNIT
	Input voltage, VI(IN)				2.7	5.5	V
	Input voltage, VI at				0	5.5	V
		EN
				TPS2010	0	0.2
	Continuous output current, IO			TPS2011	0	0.6	A
				TPS2012	0	1
				TPS2013	0	1.5
	Operating virtual junction temperature, TJ				± 40	125	°C

electrical characteristics over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 0 V (unless otherwise noted)

power switch

							TPS2010, TPS2011
	PARAMETER			TEST CONDITIONS²			TPS2012, TPS2013		UNIT
							MIN TYP	MAX
			VI(IN) = 5.5 V,		TJ = 25°C		75	95
	On-state resistance		VI(IN) = 4.5 V,		TJ = 25°C		80	110	mΩ
			VI(IN) = 3 V,		TJ = 25°C		120	175
			VI(IN) = 2.7 V,		TJ = 25°C		140	215
	Output leakage current			= VI(IN)	TJ = 25°C		0.001	1	A
			EN
					± 40°C ≤ TJ ≤ 125°C			10
tr	Output rise time		VI(IN) = 5.5 V,		TJ = 25°C,	CL = 1 F	4		ms
			VI(IN) = 2.7 V,		TJ = 25°C,	CL = 1 F	3.8
tf	Output fall time		VI(IN) = 5.5 V,		TJ = 25°C,	CL = 1 F	3.9		ms
			VI(IN) = 2.7 V,		TJ = 25°C,	CL = 1 F	3.5

² Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

enable input (EN)

							TPS2010, TPS2011
	PARAMETER		TEST CONDITIONS				TPS2012, TPS2013		UNIT
							MIN	TYP MAX
	High-level input voltage		2.7 V ≤ VI(IN) ≤ 5.5 V				2		V
	Low-level input voltage		4.5 V ≤ VI(IN) ≤ 5.5 V					0.8	V
			2.7 V ≤ VI(IN) < 4.5 V					0.4
	Input current			= 0 V or		= VI(IN)	± 0.5	0.5	A
			EN		EN
tPLH	Propagation (delay) time, low-to-high-level output		CL = 1 F					20	ms
tPHL	Propagation (delay) time, high-to-low-level output		CL = 1 F					40

current limit

				TPS2010, TPS2011
	PARAMETER	TEST CONDITIONS²		TPS2012, TPS2013			UNIT
				MIN	TYP	MAX
		TJ = 25°C,	TPS2010	0.22	0.4	0.6
			TPS2011	0.66	1.2	1.8
	Short-circuit current	VI(IN) = 5.5 V,					A
		OUT connected to GND, device	TPS2012	1.1	2	3
		enabled into short circuit
			TPS2013	1.65	2.6	4.5

² Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

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TPS2010, TPS2011, TPS2012, TPS2013

POWER-DISTRIBUTION

SLVS097A ± DECEMBER 1994 ± REVISED AUGUST 1995

electrical characteristics over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 0 V (unless otherwise noted) (continued)

supply current

							TPS2010, TPS2011
PARAMETER				TEST CONDITIONS			TPS2012, TPS2013			UNIT
							MIN	TYP	MAX
Supply current, low-level output			= VI(IN)		TJ = 25°C			0.015	1	A
		EN
					± 40°C ≤ TJ	≤ 125°C			10
					TJ = 25°C			73	100	A
Supply current, high-level output		EN = 0 V
					± 40°C ≤ TJ	≤ 125°C			100

electrical characteristics over recommended operating junction temperature range, VI(IN) = 5.5 V, IO = rated current, EN = 0 V, TJ = 25°C (unless otherwise noted)

power switch

					TPS2010Y, TPS2011Y
PARAMETER			TEST CONDITIONS²		TPS2012Y, TPS2013Y	UNIT
					MIN TYP MAX
		VI(IN) = 5.5 V,			75
On-state resistance		VI(IN) = 4.5 V,			80	mΩ
		VI(IN) = 3 V,			120
		VI(IN) = 2.7 V,			140
Output leakage current			= VI(IN)		0.001	A
		EN
Output rise time		VI(IN) = 5.5 V,		CL = 1 F	4	ms
		VI(IN) = 2.7 V,		CL = 1 F	3.8
Output fall time		VI(IN) = 5.5 V,		CL = 1 F	3.9	ms
		VI(IN) = 2.7 V,		CL = 1 F	3.5

² Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

current limit

		TPS2010Y, TPS2011Y
PARAMETER	TEST CONDITIONS²	TPS2012Y, TPS2013Y	UNIT
		MIN TYP MAX
	VI(IN) = 5.5 V,
Short-circuit current	OUT connected to GND,	0.4	A
	Device enabled into short circuit

² Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

supply current

					TPS2010Y, TPS2011Y
PARAMETER				TEST CONDITIONS	TPS2012Y, TPS2013Y			UNIT
					MIN	TYP	MAX
Supply current, low-level output				= VI(IN)		0.015		A
		EN
Supply current, high-level output				= 0 V		73		A
		EN

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