TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS233A ± JULY 1999 ± REVISED MARCH 2000
features
DDual 8-Bit Voltage Output DAC
DProgrammable Internal Reference
DProgrammable Settling Time
±2.5 s in Fast Mode
±12 s in Slow Mode
DCompatible With TMS320 and SPI Serial
Ports
DDifferential Nonlinearity <0.2 LSB Max
DMonotonic Over Temperature
description
The TLV5625 is a dual 8-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface is compatible with TMS320, SPI , QSPI , and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 8 data bits.
applications
DDigital Servo Control Loops
DDigital Offset and Gain Adjustment
DIndustrial Process Control
DMachine and Motion Control Devices
DMass Storage Devices
D PACKAGE (TOP VIEW)
DIN |
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8 |
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VDD |
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SCLK |
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2 |
7 |
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OUTB |
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REF |
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CS |
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6 |
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OUTA |
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4 |
5 |
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AGND |
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The resistor string output voltage is buffered by an x2 gain rail-to-rail output buffer. The buffer features a Class-AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation.
Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package in standard commercial and industrial temperature ranges.
AVAILABLE OPTIONS
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PACKAGE |
TA |
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SOIC |
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(D) |
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0°C to 70°C |
TLV5625CD |
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± 40°C to 85°C |
TLV5625ID |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCT PREVIEW information concerns products in the formative or |
Copyright 2000, Texas Instruments Incorporated |
design phase of development. Characteristic data and other |
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specifications are design goals. Texas Instruments reserves the right to |
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change or discontinue these products without notice. |
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
PRODUCT PREVIEW
TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS233A ± JULY 1999 ± REVISED MARCH 2000
functional block diagram
REF AGND VDD
PRODUCT PREVIEW
Power-On |
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Power and |
Reset |
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Speed Control |
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2 |
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DIN |
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8 |
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SCLK |
Serial |
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8 |
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Interface |
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and |
Buffer |
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CS |
Control |
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8 |
x2 OUTA
8-Bit |
8 |
DAC A |
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Latch |
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8-Bit |
8 |
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DAC B |
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Latch |
x2 |
OUTB |
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Terminal Functions |
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TERMINAL |
I/O/P |
DESCRIPTION |
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NAME |
NO. |
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AGND |
5 |
P |
Ground |
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3 |
I |
Chip select. Digital input active low, used to enable/disable inputs. |
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CS |
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DIN |
1 |
I |
Digital serial data input |
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OUTA |
4 |
O |
DAC A analog voltage output |
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OUTB |
7 |
O |
DAC B analog voltage output |
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REF |
6 |
I |
Analog reference voltage input |
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SCLK |
2 |
I |
Digital serial clock input |
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VDD |
8 |
P |
Positive power supply |
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2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS233A ± JULY 1999 ± REVISED MARCH 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . 7 |
V |
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
± 0.3 V to VDD + 0.3 |
V |
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
± 0.3 V to VDD + 0.3 |
V |
Operating free-air temperature range, TA: TLV5625C . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 0°C to 70°C |
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TLV5625I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . ±40°C to 85°C |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . ±65°C to 150°C |
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Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . 260°C |
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²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
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MIN |
NOM |
MAX |
UNIT |
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Supply voltage, VDD |
VDD = 5 V |
4.5 |
5 |
5.5 |
V |
VDD = 3 V |
2.7 |
3 |
3.3 |
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Power on reset, POR |
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0.55 |
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2 |
V |
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High-level digital input voltage, VIH |
VDD = 2.7 V to 5.5 V |
2 |
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V |
Low-level digital input voltage, VIL |
VDD = 2.7 V to 5.5 V |
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0.8 |
V |
Reference voltage, Vref to REF terminal |
VDD = 5 V (see Note 1) |
AGND |
2.048 |
VDD ±1.5 |
V |
Reference voltage, Vref to REF terminal |
VDD = 3 V (see Note 1) |
AGND |
1.024 |
VDD ± 1.5 |
V |
Load resistance, RL |
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2 |
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kΩ |
Load capacitance, CL |
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100 |
pF |
Clock frequency, fCLK |
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20 |
MHz |
Operating free-air temperature, TA |
TLV5625C |
0 |
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70 |
°C |
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TLV5625I |
±40 |
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85 |
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NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD±0.4 V)/2 causes clipping of the transfer function.
PRODUCT PREVIEW
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
PRODUCT PREVIEW
TLV5625
2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS233A ± JULY 1999 ± REVISED MARCH 2000
electrical characteristics over recommended operating conditions (unless otherwise noted)
power supply
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PARAMETER |
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TEST CONDITIONS |
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MIN TYP |
MAX |
UNIT |
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IDD |
Power supply current |
No load, |
All inputs = AGND or VDD, |
Fast |
1.8 |
2.3 |
mA |
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DAC latch |
= 0x800 |
Slow |
0.8 |
1 |
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Power-down supply current |
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1 |
3 |
µA |
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PSRR |
Power supply rejection ratio |
Zero scale, See Note 2 |
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±65 |
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dB |
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Full scale, |
See Note 3 |
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±65 |
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NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:
PSRR = 20 log [(EZS(VDDmax) ± EZS(VDDmin)/VDDmax]
3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) ± EG(VDDmin)/VDDmax]
static DAC specifications
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PARAMETER |
TEST CONDITIONS |
MIN TYP |
MAX |
UNIT |
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Resolution |
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8 |
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bits |
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INL |
Integral nonlinearity |
See Note 4 |
± 0.3 |
± 0.5 |
LSB |
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DNL |
Differential nonlinearity |
See Note 5 |
± 0.07 |
± 0.2 |
LSB |
EZS |
Zero-scale error (offset error at zero scale) |
See Note 6 |
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± 12 |
mV |
EZS TC |
Zero-scale-error temperature coefficient |
See Note 7 |
10 |
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ppm/°C |
EG |
Gain error |
See Note 8 |
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± 0.5 |
% full |
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scale V |
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EG TC |
Gain-error temperature coefficient |
See Note 9 |
10 |
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ppm/°C |
NOTES: 4. The relative accuracy of integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale, excluding the effects of zero-code and full-scale errors.
5.The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1-LSB amplitude change of any two adjacent codes.
6.Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7.Zero-scale error temperature coefficient is given by: EZS TC = [EZS (Tmax) ± EZS (Tmin)]/2Vref ×106/(Tmax ± Tmin).
8.Gain error is the deviation from the ideal output (2Vref ± 1 LSB) with an output load of 10 kΩ.
9.Gain temperature coefficient is given by: EG TC = [EG (Tmax) ± Eg (Tmin)]/2Vref ×106/(Tmax ± Tmin).
output specifications
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PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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VO |
Output voltage range |
RL = 10 kΩ |
0 |
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VDD±0.4 |
V |
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Output load regulation accuracy |
VO = 4.096 V, 2.048 V RL = 2 kΩ |
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± 0.29 |
% FS |
reference input
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PARAMETER |
TEST CONDITIONS |
MIN TYP |
MAX |
UNIT |
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VI |
Input voltage range |
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0 |
VDD±1.5 |
V |
RI |
Input resistance |
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10 |
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MΩ |
CI |
Input capacitance |
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5 |
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pF |
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Reference input bandwidth |
REF = 0.2 Vpp + 1.024 V dc |
Fast |
1.3 |
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MHz |
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Slow |
525 |
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kHz |
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Reference feedthrough |
REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) |
± 80 |
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dB |
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NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
4 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TLV5625 2.7-V TO 5.5-V LOW-POWER DUAL 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN
SLAS233A ± JULY 1999 ± REVISED MARCH 2000
electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued)
digital inputs
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PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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IIH |
High-level digital input current |
VI = VDD |
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1 |
µA |
IIL |
Low-level digital input current |
VI = 0 V |
±1 |
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µA |
Ci |
Input capacitance |
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8 |
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pF |
analog output dynamic performance
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PARAMETER |
TEST CONDITIONS |
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MIN |
TYP |
MAX |
UNIT |
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ts(FS) |
Output settling time, full scale |
RL = 10 kΩ, |
CL = 100 pF, |
Fast |
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2.5 |
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µs |
See Note 11 |
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Slow |
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12 |
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ts(CC) |
Output settling time, code to code |
RL = 10 kΩ, |
CL = 100 pF, |
Fast |
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1 |
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µs |
See Note 12 |
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Slow |
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2 |
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SR |
Slew rate |
RL = 10 kΩ, |
CL = 100 pF, |
Fast |
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3 |
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V/µs |
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Slow |
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0.5 |
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See Note 13 |
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Glitch energy |
DIN = 0 to 1, FCLK = 100 kHz, |
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5 |
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nV±s |
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CS = VDD |
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SNR |
Signal-to-noise ratio |
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52 |
54 |
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SINAD |
Signal-to-noise + distortion |
fs = 102 kSPS, |
fout = 1 kHz, |
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48 |
49 |
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dB |
THD |
Total harmonic distortion |
RL = 10 kΩ, |
CL = 100 pF |
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±50 |
±48 |
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SFDR |
Spurious free dynamic range |
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48 |
50 |
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NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.
12.Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design.
13.Slew rate determines the time it takes for a change of the DAC output from 10% to 90% of full-scale voltage.
PRODUCT PREVIEW
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
5 |
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