Texas instruments TMS320F28332, TMS320F28232, TMS320F28235, TMS320F28234, TMS320F28334 Data Manual

TMS320F28335, TMS320F28334, TMS320F28332 TMS320F28235, TMS320F28234, TMS320F28232

Digital Signal Controllers (DSCs)

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SPRS439I

June 2007 –Revised March 2011

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011 www.ti.com

			Contents
1	TMS320F2833x, TMS320F2823x DSCs ..................................................................................			11
	1.1	Features	....................................................................................................................	11
	1.2	Getting Started .............................................................................................................		12
2	Introduction ......................................................................................................................			13
	2.1	Pin Assignments ...........................................................................................................		15
	2.2	Signal Descriptions ........................................................................................................		24
3	Functional Overview ..........................................................................................................			34
	3.1	Memory Maps ..............................................................................................................		35
	3.2	Brief Descriptions ..........................................................................................................		42
		3.2.1	C28x CPU .......................................................................................................	42
		3.2.2	Memory Bus (Harvard Bus Architecture) ....................................................................	42
		3.2.3	Peripheral Bus ..................................................................................................	42
		3.2.4	Real-Time JTAG and Analysis ................................................................................	43
		3.2.5	External Interface (XINTF) ....................................................................................	43
		3.2.6	Flash .............................................................................................................	43
		3.2.7	M0, M1 SARAMs ...............................................................................................	43
		3.2.8	L0, L1, L2, L3, L4, L5, L6, L7 SARAMs .....................................................................	44
		3.2.9	Boot ROM ........................................................................................................	44
			3.2.9.1 Peripheral Pins Used by the Bootloader ........................................................	45
		3.2.10	Security ..........................................................................................................	45
		3.2.11	Peripheral Interrupt Expansion (PIE) Block .................................................................	47
		3.2.12	External Interrupts (XINT1–XINT7, XNMI) ..................................................................	47
		3.2.13	Oscillator and PLL ..............................................................................................	47
		3.2.14	Watchdog ........................................................................................................	47
		3.2.15	Peripheral Clocking .............................................................................................	47
		3.2.16	Low-Power Modes ..............................................................................................	47
		3.2.17	Peripheral Frames 0, 1, 2, 3 (PFn) ...........................................................................	48
		3.2.18	General-Purpose Input/Output (GPIO) Multiplexer .........................................................	48
		3.2.19	32-Bit CPU-Timers (0, 1, 2) ...................................................................................	48
		3.2.20	Control Peripherals .............................................................................................	49
		3.2.21	Serial Port Peripherals .........................................................................................	49
	3.3	Register Map ...............................................................................................................		50
	3.4	Device Emulation Registers ..............................................................................................		52
	3.5	Interrupts ....................................................................................................................		53
		3.5.1	External Interrupts ..............................................................................................	57
	3.6	System Control ............................................................................................................		58
		3.6.1	OSC and PLL Block ............................................................................................	59
			3.6.1.1 External Reference Oscillator Clock Option ....................................................	60
			3.6.1.2 PLL-Based Clock Module .........................................................................	61
			3.6.1.3 Loss of Input Clock ................................................................................	62
		3.6.2	Watchdog Block .................................................................................................	63
	3.7	Low-Power Modes Block .................................................................................................		64
4	Peripherals .......................................................................................................................			65
	4.1	DMA Overview .............................................................................................................		65
	4.2	32-Bit CPU-Timers 0/1/2 .................................................................................................		67

2

Contents

Copyright © 2007–2011, Texas Instruments Incorporated

			TMS320F28335, TMS320F28334, TMS320F28332
			TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com				SPRS439I –JUNE 2007 –REVISED MARCH 2011
	4.3	Enhanced PWM Modules (ePWM1/2/3/4/5/6 ) ........................................................................			69
	4.4	High-Resolution PWM (HRPWM) .......................................................................................			73
	4.5	Enhanced CAP Modules (eCAP1/2/3/4/5/6) ...........................................................................			74
	4.6	Enhanced QEP Modules (eQEP1/2 ) ...................................................................................			76
	4.7	Analog-to-Digital Converter (ADC) Module ............................................................................			78
		4.7.1	ADC Connections if the ADC Is Not Used ..................................................................		82
		4.7.2	ADC Registers ..................................................................................................		83
		4.7.3	ADC Calibration .................................................................................................		84
	4.8	Multichannel Buffered Serial Port (McBSP) Module ..................................................................			84
	4.9	Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B)			.................................... 87
	4.10	Serial Communications Interface (SCI) Modules (SCI-A, SCI-B, SCI-C) ..........................................			92
	4.11	Serial Peripheral Interface (SPI) Module (SPI-A ) .....................................................................			96
	4.12	Inter-Integrated Circuit (I2C) .............................................................................................			99
	4.13	GPIO MUX ................................................................................................................			100
	4.14	External Interface (XINTF) ..............................................................................................			107
5	Device Support ................................................................................................................				109
	5.1	Device and Development Support Tool Nomenclature .............................................................			109
	5.2	Documentation Support .................................................................................................			111
	5.3	Community Resources ..................................................................................................			116
6	Electrical Specifications ...................................................................................................				117
	6.1	Absolute Maximum Ratings .............................................................................................			117
	6.2	Recommended Operating Conditions .................................................................................			118
	6.3	Electrical Characteristics ................................................................................................			118
	6.4	Current Consumption ....................................................................................................			119
		6.4.1	Reducing Current Consumption .............................................................................		121
		6.4.2	Current Consumption Graphs ...............................................................................		122
		6.4.3	Thermal Design Considerations .............................................................................		123
	6.5	Emulator Connection Without Signal Buffering for the DSP .......................................................			124
	6.6	Timing Parameter Symbology ..........................................................................................			125
		6.6.1	General Notes on Timing Parameters ......................................................................		125
		6.6.2	Test Load Circuit ..............................................................................................		125
		6.6.3	Device Clock Table ...........................................................................................		126
	6.7	Clock Requirements and Characteristics .............................................................................			127
	6.8	Power Sequencing .......................................................................................................			128
		6.8.1	Power Management and Supervisory Circuit Solutions ..................................................		128
	6.9	General-Purpose Input/Output (GPIO) ................................................................................			131
		6.9.1	GPIO - Output Timing ........................................................................................		131
		6.9.2	GPIO - Input Timing ..........................................................................................		132
		6.9.3	Sampling Window Width for Input Signals .................................................................		133
		6.9.4	Low-Power Mode Wakeup Timing ..........................................................................		134
	6.10	Enhanced Control Peripherals .........................................................................................			139
		6.10.1	Enhanced Pulse Width Modulator (ePWM) Timing .......................................................		139
		6.10.2	Trip-Zone Input Timing .......................................................................................		139
		6.10.3	Enhanced Capture (eCAP) Timing .........................................................................		140
		6.10.4	Enhanced Quadrature Encoder Pulse (eQEP) Timing ...................................................		140
		6.10.5	ADC Start-of-Conversion Timing ............................................................................		141
	6.11	External Interrupt Timing ................................................................................................			141

Copyright © 2007–2011, Texas Instruments Incorporated

Contents

3

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011							www.ti.com
	6.12	I2C Electrical Specification and Timing ...............................................................................					142
	6.13	Serial Peripheral Interface (SPI) Timing ..............................................................................					142
		6.13.1	Master Mode Timing ..........................................................................................				142
		6.13.2 SPI Slave Mode Timing ......................................................................................					147
	6.14	External Interface (XINTF) Timing .....................................................................................					150
		6.14.1	USEREADY = 0 ...............................................................................................				150
		6.14.2 Synchronous Mode (USEREADY = 1, READYMODE = 0) .............................................					151
		6.14.3 Asynchronous Mode (USEREADY = 1, READYMODE = 1) ............................................					152
		6.14.4 XINTF Signal Alignment to XCLKOUT .....................................................................					154
		6.14.5 External Interface Read Timing .............................................................................					155
		6.14.6 External Interface Write Timing .............................................................................					157
		6.14.7 External Interface Ready-on-Read Timing With One External Wait State ............................					159
		6.14.8 External Interface Ready-on-Write Timing With One External Wait State .............................					162
		6.14.9		and		Timing	165
			XHOLD		XHOLDA
	6.15	On-Chip Analog-to-Digital Converter ..................................................................................					168
		6.15.1 ADC Power-Up Control Bit Timing ..........................................................................					169
		6.15.2	Definitions ......................................................................................................				170
		6.15.3 Sequential Sampling Mode (Single-Channel) (SMODE = 0) ............................................					171
		6.15.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) ..........................................					172
		6.15.5	Detailed Descriptions .........................................................................................				173
	6.16	Multichannel Buffered Serial Port (McBSP) Timing .................................................................					174
		6.16.1 McBSP Transmit and Receive Timing ......................................................................					174
		6.16.2 McBSP as SPI Master or Slave Timing ....................................................................					177
	6.17	Flash Timing ..............................................................................................................					181
	6.18	Migrating Between F2833x Devices and F2823x Devices .........................................................					182
7	Revision History ..............................................................................................................						183
8	Thermal/Mechanical Data ..................................................................................................						184

4

Contents

Copyright © 2007–2011, Texas Instruments Incorporated

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

www.ti.com SPRS439I –JUNE 2007 –REVISED MARCH 2011

List of Figures

2-1	F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View) ......................................................................		15
2-2	F2833x, F2823x 179-Ball ZHH MicroStar BGA™	(Upper Left Quadrant) (Bottom View) ..............................	17
2-3	F2833x, F2823x 179-Ball ZHH MicroStar BGA™	(Upper Right Quadrant) (Bottom View).............................	18
2-4	F2833x, F2823x 179-Ball ZHH MicroStar BGA™	(Lower Left Quadrant) (Bottom View) ..............................	19
2-5	F2833x, F2823x 179-Ball ZHH MicroStar BGA ™ (Lower Right Quadrant) (Bottom View).............................		20
2-6	F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Left Quadrant) (Bottom View)......................................		21
2-7	F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Right Quadrant) (Bottom View) ....................................		22
2-8	F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Left Quadrant) (Bottom View)......................................		23
2-9	F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Right Quadrant) (Bottom View) ....................................		23
3-1	Functional Block Diagram ......................................................................................................		35
3-2	F28335/F28235 Memory Map .................................................................................................		37
3-3	F28334/F28234 Memory Map .................................................................................................		38
3-4	F28332/F28232 Memory Map .................................................................................................		38
3-5	External and PIE Interrupt Sources ............................................................................................		54
3-6	External Interrupts................................................................................................................		54
3-7	Multiplexing of Interrupts Using the PIE Block ...............................................................................		55
3-8	Clock and Reset Domains ......................................................................................................		58
3-9	OSC and PLL Block Diagram...................................................................................................		59
3-10	Using a 3.3-V External Oscillator...............................................................................................		60
3-11	Using a 1.9 -V External Oscillator..............................................................................................		60
3-12	Using the Internal Oscillator ....................................................................................................		60
3-13	Watchdog Module ................................................................................................................		63
4-1	DMA Functional Block Diagram ................................................................................................		66
4-2	CPU-Timers .......................................................................................................................		67
4-3	CPU-Timer Interrupt Signals and Output Signal .............................................................................		67
4-4	Multiple PWM Modules in an 2833x/2823x System .........................................................................		69
4-5	ePWM Submodules Showing Critical Internal Signal Interconnections ...................................................		72
4-6	eCAP Functional Block Diagram ...............................................................................................		74
4-7	eQEP Functional Block Diagram ...............................................................................................		76
4-8	Block Diagram of the ADC Module ............................................................................................		79
4-9	ADC Pin Connections With Internal Reference ..............................................................................		80
4-10	ADC Pin Connections With External Reference .............................................................................		81
4-11	McBSP Module ..................................................................................................................		85
4-12	eCAN Block Diagram and Interface Circuit ...................................................................................		88
4-13	eCAN-A Memory Map ...........................................................................................................		89
4-14	eCAN-B Memory Map ...........................................................................................................		90
4-15	Serial Communications Interface (SCI) Module Block Diagram............................................................		95
4-16	SPI Module Block Diagram (Slave Mode) ....................................................................................		98
4-17	I2C Peripheral Module Interfaces ..............................................................................................		99
4-18	GPIO MUX Block Diagram ....................................................................................................		101
4-19	Qualification Using Sampling Window .......................................................................................		106
4-20	External Interface Block Diagram.............................................................................................		107
4-21	Typical 16-bit Data Bus XINTF Connections................................................................................		108
4-22	Typical 32-bit Data Bus XINTF Connections................................................................................		108
5-1	Example of F2833x, F2823x Device Nomenclature........................................................................		110
6-1	Typical Operational Current Versus Frequency (F28335/F28235/F28334/F28234) ...................................		123
6-2	Typical Operational Power Versus Frequency (F28335/F28235/F28334/F28234) ....................................		123

Copyright © 2007–2011, Texas Instruments Incorporated

List of Figures

5

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011								www.ti.com
6-3	Emulator Connection Without Signal Buffering for the DSP .............................................................							124
6-4	3.3-V Test Load Circuit.........................................................................................................							125
6-5	Clock Timing.....................................................................................................................							128
6-6	Power-on Reset .................................................................................................................							129
6-7	Warm Reset .....................................................................................................................							130
6-8	Example of Effect of Writing Into PLLCR Register .........................................................................							131
6-9	General-Purpose Output Timing ..............................................................................................							132
6-10	Sampling Mode .................................................................................................................							132
6-11	General-Purpose Input Timing ................................................................................................							133
6-12	IDLE Entry and Exit Timing....................................................................................................							134
6-13	STANDBY Entry and Exit Timing Diagram ..................................................................................							136
6-14	HALT Wake-Up Using GPIOn.................................................................................................							138
6-15	PWM Hi-Z Characteristics .....................................................................................................							139
6-16				or			Timing	141
	ADCSOCAO				ADCSOCBO
6-17	External Interrupt Timing.......................................................................................................							141
6-18	SPI Master Mode External Timing (Clock Phase = 0) .....................................................................							144
6-19	SPI Master Mode External Timing (Clock Phase = 1) .....................................................................							146
6-20	SPI Slave Mode External Timing (Clock Phase = 0).......................................................................							148
6-21	SPI Slave Mode External Timing (Clock Phase = 1).......................................................................							149
6-22	Relationship Between XTIMCLK and SYSCLKOUT .......................................................................							153
6-23	Example Read Access .........................................................................................................							156
6-24	Example Write Access .........................................................................................................							158
6-25	Example Read With Synchronous XREADY Access ......................................................................							160
6-26	Example Read With Asynchronous XREADY Access .....................................................................							161
6-27	Write With Synchronous XREADY Access ..................................................................................							163
6-28	Write With Asynchronous XREADY Access ................................................................................							164
6-29	External Interface Hold Waveform............................................................................................							166
6-30								167
	XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) ..................................................
6-31	ADC Power-Up Control Bit Timing ...........................................................................................							169
6-32	ADC Analog Input Impedance Model ........................................................................................							170
6-33	Sequential Sampling Mode (Single-Channel) Timing ......................................................................							171
6-34	Simultaneous Sampling Mode Timing .......................................................................................							172
6-35	McBSP Receive Timing ........................................................................................................							176
6-36	McBSP Transmit Timing .......................................................................................................							176
6-37	McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0 ...................................................							177
6-38	McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0 ...................................................							178
6-39	McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1 ...................................................							179
6-40	McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1 ...................................................							180

6

List of Figures

Copyright © 2007–2011, Texas Instruments Incorporated

	TMS320F28335, TMS320F28334, TMS320F28332
	TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com		SPRS439I –JUNE 2007 –REVISED MARCH 2011
	List of Tables
2-1	F2833x Hardware Features ....................................................................................................		13
2-2	F2823x Hardware Features ....................................................................................................		14
2-3	Signal Descriptions...............................................................................................................		24
3-1	Addresses of Flash Sectors in F28335/F28235 .............................................................................		39
3-2	Addresses of Flash Sectors in F28334/F28234 ..............................................................................		39
3-3	Addresses of Flash Sectors in F28332/F28232 ..............................................................................		39
3-4	Handling Security Code Locations .............................................................................................		40
3-5	Wait-states ........................................................................................................................		41
3-6	Boot Mode Selection.............................................................................................................		44
3-7	Peripheral Bootload Pins ........................................................................................................		45
3-8	Peripheral Frame 0 Registers ..................................................................................................		50
3-9	Peripheral Frame 1 Registers ..................................................................................................		50
3-10	Peripheral Frame 2 Registers ..................................................................................................		51
3-11	Peripheral Frame 3 Registers ..................................................................................................		51
3-12	Device Emulation Registers.....................................................................................................		52
3-13	PIE Peripheral Interrupts .......................................................................................................		55
3-14	PIE Configuration and Control Registers......................................................................................		56
3-15	External Interrupt Registers .....................................................................................................		57
3-16	PLL, Clocking, Watchdog, and Low-Power Mode Registers ...............................................................		59
3-17	PLL Settings ......................................................................................................................		61
3-18	CLKIN Divide Options ...........................................................................................................		61
3-19	Possible PLL Configuration Modes ............................................................................................		62
3-20	Low-Power Modes ...............................................................................................................		64
4-1	CPU-Timers 0, 1, 2 Configuration and Control Registers...................................................................		68
4-2	ePWM Control and Status Registers (Default Configuration in PF1)......................................................		70
4-3	ePWM Control and Status Registers (Remapped Configuration in PF3 - DMA-Accessible)...........................		71
4-4	eCAP Control and Status Registers ...........................................................................................		75
4-5	eQEP Control and Status Registers ...........................................................................................		77
4-6	ADC Registers ...................................................................................................................		83
4-7	McBSP Register Summary......................................................................................................		86
4-8	3.3-V eCAN Transceivers ......................................................................................................		88
4-9	CAN Register Map ..............................................................................................................		91
4-10	SCI-A Registers ..................................................................................................................		93
4-11	SCI-B Registers ..................................................................................................................		93
4-12	SCI-C Registers .................................................................................................................		94
4-13	SPI-A Registers...................................................................................................................		97
4-14	I2C-A Registers .................................................................................................................		100
4-15	GPIO Registers .................................................................................................................		102
4-16	GPIO-A Mux Peripheral Selection Matrix ...................................................................................		103
4-17	GPIO-B Mux Peripheral Selection Matrix ...................................................................................		104
4-18	GPIO-C Mux Peripheral Selection Matrix ...................................................................................		105
4-19	XINTF Configuration and Control Register Mapping .......................................................................		108
5-1	TMS320x2833x, 2823x Peripheral Selection Guide .......................................................................		111
6-1	TMS320F28335/F28235 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT .................		119
6-2	TMS320F28334/F28234 Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT .................		120
6-3	Typical Current Consumption by Various Peripherals (at 150 MHz) ....................................................		121
6-4	Clocking and Nomenclature (150-MHz Devices) ...........................................................................		126

Copyright © 2007–2011, Texas Instruments Incorporated

List of Tables

7

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011							www.ti.com
6-5	Clocking and Nomenclature (100-MHz Devices) ...........................................................................						126
6-6	Input Clock Frequency .........................................................................................................						127
6-7	XCLKIN Timing Requirements – PLL Enabled .............................................................................						127
6-8	XCLKIN Timing Requirements – PLL Disabled ............................................................................						127
6-9	XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) ......................................................						127
6-10	Power Management and Supervisory Circuit Solutions ...................................................................						128
6-11	Reset				Timing Requirements		130
		(XRS)
6-12	General-Purpose Output Switching Characteristics ........................................................................						131
6-13	General-Purpose Input Timing Requirements ..............................................................................						132
6-14	IDLE Mode Timing Requirements ...........................................................................................						134
6-15	IDLE Mode Switching Characteristics .......................................................................................						134
6-16	STANDBY Mode Timing Requirements .....................................................................................						135
6-17	STANDBY Mode Switching Characteristics ................................................................................						135
6-18	HALT Mode Timing Requirements ...........................................................................................						137
6-19	HALT Mode Switching Characteristics ......................................................................................						137
6-20	ePWM Timing Requirements .................................................................................................						139
6-21	ePWM Switching Characteristics ............................................................................................						139
6-22	Trip-Zone Input Timing Requirements ......................................................................................						139
6-23	High-Resolution PWM Characteristics at SYSCLKOUT = (60 –150 MHz)..............................................						140
6-24	Enhanced Capture (eCAP) Timing Requirement ..........................................................................						140
6-25	eCAP Switching Characteristics .............................................................................................						140
6-26	Enhanced Quadrature Encoder Pulse (eQEP) Timing Requirements ..................................................						140
6-27	eQEP Switching Characteristics .............................................................................................						140
6-28	External ADC Start-of-Conversion Switching Characteristics.............................................................						141
6-29	External Interrupt Timing Requirements ....................................................................................						141
6-30	External Interrupt Switching Characteristics ................................................................................						141
6-31	I2C Timing ......................................................................................................................						142
6-32	SPI Master Mode External Timing (Clock Phase = 0) ....................................................................						143
6-33	SPI Master Mode External Timing (Clock Phase = 1) ....................................................................						145
6-34	SPI Slave Mode External Timing (Clock Phase = 0) ......................................................................						147
6-35	SPI Slave Mode External Timing (Clock Phase = 1) ......................................................................						149
6-36	Relationship Between Parameters Configured in XTIMING and Duration of Pulse ...................................						150
6-37	XINTF Clock Configurations ..................................................................................................						153
6-38	External Interface Read Timing Requirements .............................................................................						155
6-39	External Interface Read Switching Characteristics .........................................................................						155
6-40	External Interface Write Switching Characteristics .........................................................................						157
6-41	External Interface Read Switching Characteristics (Ready-on-Read, 1 Wait State) ...................................						159
6-42	External Interface Read Timing Requirements (Ready-on-Read, 1 Wait State) .......................................						159
6-43	Synchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State) .......................................						159
6-44	Asynchronous XREADY Timing Requirements (Ready-on-Read, 1 Wait State).......................................						159
6-45	External Interface Write Switching Characteristics (Ready-on-Write, 1 Wait State) ...................................						162
6-46	Synchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) .......................................						162
6-47	Asynchronous XREADY Timing Requirements (Ready-on-Write, 1 Wait State) ......................................						162
6-48							166
	XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ......................................................
6-49							167
	XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK) .................................................
6-50	ADC Electrical Characteristics (over recommended operating conditions) ............................................						168
6-51	ADC Power-Up Delays.........................................................................................................						169
6-52	Typical Current Consumption for Different ADC Configurations (at 25-MHz ADCCLK) ..............................						169

8

List of Tables

Copyright © 2007–2011, Texas Instruments Incorporated

		TMS320F28335, TMS320F28334, TMS320F28332
		TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com		SPRS439I –JUNE 2007 –REVISED MARCH 2011
6-53	Sequential Sampling Mode Timing ...........................................................................................		171
6-54	Simultaneous Sampling Mode Timing .......................................................................................		172
6-55	McBSP Timing Requirements ................................................................................................		174
6-56	McBSP Switching Characteristics ...........................................................................................		175
6-57	McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0) ................................		177
6-58	McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)............................		177
6-59	McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 0) ................................		178
6-60	McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 0)............................		178
6-61	McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1) ................................		179
6-62	McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)............................		179
6-63	McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1) ................................		180
6-64	McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1) ...........................		180
6-65	Flash Endurance for A and S Temperature Material ......................................................................		181
6-66	Flash Endurance for Q Temperature Material ..............................................................................		181
6-67	Flash Parameters at 150-MHz SYSCLKOUT ...............................................................................		181
6-68	Flash/OTP Access Timing .....................................................................................................		181
6-69	Minimum Required Flash/OTP Wait-States at Different Frequencies ...................................................		181
8-1	Thermal Model 176-Pin PGF Results ........................................................................................		184
8-2	Thermal Model 176-Pin PTP Results ........................................................................................		184
8-3	Thermal Model 179-Ball ZHH Results .......................................................................................		184
8-4	Thermal Model 176-Ball ZJZ Results .......................................................................................		185

Copyright © 2007–2011, Texas Instruments Incorporated

List of Tables

9

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011

www.ti.com

10

List of Tables

Copyright © 2007–2011, Texas Instruments Incorporated

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

www.ti.com

SPRS439I –JUNE 2007 –REVISED MARCH 2011

Digital Signal Controllers (DSCs)

Check for Samples: TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, TMS320F28232

1 TMS320F2833x, TMS320F2823x DSCs

1.1Features

•High-Performance Static CMOS Technology

–Up to 150 MHz (6.67-ns Cycle Time)

–1.9-V/1.8 -V Core, 3.3-V I/O Design

•High-Performance 32-Bit CPU (TMS320C28x)

–IEEE-754 Single-Precision Floating-Point Unit (FPU) (F2833x only)

–16 x 16 and 32 x 32 MAC Operations

–16 x 16 Dual MAC

–Harvard Bus Architecture

–Fast Interrupt Response and Processing

–Unified Memory Programming Model

–Code-Efficient (in C/C++ and Assembly)

•Six-Channel DMA Controller (for ADC, McBSP, ePWM, XINTF, and SARAM)

•16-Bit or 32-Bit External Interface (XINTF)

–Over 2M x 16 Address Reach

•On-Chip Memory

–F28335/F28235: 256K x 16 Flash, 34K x 16 SARAM

–F28334/F28234: 128K x 16 Flash, 34K x 16 SARAM

–F28332/F28232: 64K x 16 Flash, 26K x 16 SARAM

–1K x 16 OTP ROM

•Boot ROM (8K x 16)

–With Software Boot Modes (via SCI, SPI, CAN, I2C, McBSP, XINTF, and Parallel I/O)

–Standard Math Tables

•Clock and System Control

–Dynamic PLL Ratio Changes Supported

–On-Chip Oscillator

–Watchdog Timer Module

•GPIO0 to GPIO63 Pins Can Be Connected to One of the Eight External Core Interrupts

•Peripheral Interrupt Expansion (PIE) Block That Supports All 58 Peripheral Interrupts

•128-Bit Security Key/Lock

–Protects Flash/OTP/RAM Blocks

–Prevents Firmware Reverse Engineering

•Enhanced Control Peripherals

–Up to 18 PWM Outputs

–Up to 6 HRPWM Outputs With 150 ps MEP Resolution

–Up to 6 Event Capture Inputs

–Up to 2 Quadrature Encoder Interfaces

–Up to 8 32-Bit/Nine 16-Bit Timers

•Three 32-Bit CPU Timers

•Serial Port Peripherals

–Up to 2 CAN Modules

–Up to 3 SCI (UART) Modules

–Up to 2 McBSP Modules (Configurable as SPI)

–One SPI Module

–One Inter-Integrated-Circuit (I2C) Bus

•12-Bit ADC, 16 Channels

–80-ns Conversion Rate

–2 x 8 Channel Input Multiplexer

–Two Sample-and-Hold

–Single/Simultaneous Conversions

–Internal or External Reference

•Up to 88 Individually Programmable, Multiplexed GPIO Pins With Input Filtering

•JTAG Boundary Scan Support (1)

•Advanced Emulation Features

–Analysis and Breakpoint Functions

–Real-Time Debug via Hardware

•Development Support Includes

–ANSI C/C++ Compiler/Assembler/Linker

–Code Composer Studio™ IDE

–DSP/BIOS™

–Digital Motor Control and Digital Power Software Libraries

•Low-Power Modes and Power Savings

–IDLE, STANDBY, HALT Modes Supported

–Disable Individual Peripheral Clocks

(1)IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MicroStar BGA, Code Composer Studio, DSP/BIOS, TMS320C28x, Delfino, PowerPAD, TMS320C54x, TMS320C55x, C28x are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is	current as of publication date.	Copyright © 2007–2011, Texas Instruments Incorporated
Products conform to specifications	per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011			www.ti.com
• Package Options:		• Temperature Options:
–	Lead-free, Green Packaging	–	A: –40°C to 85°C (PGF, ZHH, ZJZ)
–	Low-Profile Quad Flatpack (PGF, PTP)	–	S: –40°C to 125°C (PTP, ZJZ)
–	MicroStar BGA™ (ZHH)	–	Q: –40°C to 125°C (PTP, ZJZ)

–Plastic BGA (ZJZ)

1.2Getting Started

This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following:

•Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0).

•C2000 Getting Started Website (http://www.ti.com/c2000getstarted)

•TMS320F28x DSC Development and Experimenter'sKits (http://www.ti.com/f28xkits)

12

TMS320F2833x, TMS320F2823x DSCs

Copyright © 2007–2011, Texas Instruments Incorporated

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TMS320F28232

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

www.ti.com

SPRS439I –JUNE 2007 –REVISED MARCH 2011

2 Introduction

The TMS320F28335, TMS320F28334, TMS320F28332, TMS320F28235, TMS320F28234, and TMS320F28232 devices, members of the TMS320C28x™ / Delfino™ DSC/MCU generation, are highly integrated, high-performance solutions for demanding control applications.

Throughout this document, the devices are abbreviated as F28335, F28334, F28332, F28235, F28234, and F28232, respectively. Table 2-1 and Table 2-2 provide a summary of features for each device.

Table 2-1. F2833x Hardware Features

	FEATURE			TYPE(1)	F28335 (150 MHz)	F28334 (150 MHz)	F28332 (100 MHz)
	Instruction cycle			–	6.67 ns	6.67 ns	10 ns
	Floating-point Unit			–	Yes	Yes	Yes
	3.3-V on-chip flash (16-bit word)			–	256K	128K	64K
	Single-access RAM (SARAM) (16-bit word)			–	34K	34K	26K
	One-time programmable (OTP) ROM			–	1K	1K	1K
	(16-bit word)
	Code security for on-chip			–	Yes	Yes	Yes
	flash/SARAM/OTP blocks
	Boot ROM (8K x 16)			–	Yes	Yes	Yes
	16/32-bit External Interface (XINTF)			1	Yes	Yes	Yes
	6-channel Direct Memory Access (DMA)			0	Yes	Yes	Yes
	PWM outputs			0	ePWM1/2/3/4/5/6	ePWM1/2/3/4/5/6	ePWM1/2/3/4/5/6
	HRPWM channels			0	ePWM1A/2A/3A/4A/5A/6A	ePWM1A/2A/3A/4A/5A/	ePWM1A/2A/3A/4A
						6A
	32-bit Capture inputs or auxiliary PWM			0	eCAP1/2/3/4/5/6	eCAP1/2/3/4	eCAP1/2/3/4
	outputs
	32-bit QEP channels (four inputs/channel)			0	eQEP1/2	eQEP1/2	eQEP1/2
	Watchdog timer			–	Yes	Yes	Yes
			No. of channels		16	16	16
	12-Bit ADC		MSPS	2	12.5	12.5	12.5
			Conversion time		80 ns	80 ns	80 ns
	32-Bit CPU timers			–	3	3	3
	Multichannel Buffered Serial Port			1	2 (A/B)	2 (A/B)	1 (A)
	(McBSP)/SPI
	Serial Peripheral Interface (SPI)			0	1	1	1
	Serial Communications Interface (SCI)			0	3 (A/B/C)	3 (A/B/C)	2 (A/B)
	Enhanced Controller Area Network (eCAN)			0	2 (A/B)	2 (A/B)	2 (A/B)
	Inter-Integrated Circuit (I2C)			0	1	1	1
	General Purpose I/O pins (shared)			–	88	88	88
	External interrupts			–	8	8	8
			176-Pin PGF	–	Yes	Yes	Yes
	Packaging		176-Pin PTP	–	Yes	Yes	Yes
			179-Ball ZHH	–	Yes	Yes	Yes
			176-Ball ZJZ	–	Yes	Yes	Yes
			A: –40°C to 85°C	–	(PGF, ZHH, ZJZ)	(PGF, ZHH, ZJZ)	(PGF, ZHH, ZJZ)
	Temperature		S: –40°C to 125°C	–	(PTP, ZJZ)	(PTP, ZJZ)	(PTP, ZJZ)
	options
			Q: –40°C to 125°C	–	(PTP, ZJZ)	(PTP, ZJZ)	(PTP, ZJZ)
			(Q100 Qualification)

(1)A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the

TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides.

Copyright © 2007–2011, Texas Instruments Incorporated

Introduction

13

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TMS320F28232

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011 www.ti.com

	Table 2-1. F2833x Hardware Features			(continued)
FEATURE		TYPE(1)	F28335 (150 MHz)		F28334 (150 MHz)	F28332 (100 MHz)
Product status(2)		–	TMS		TMS	TMS

(2)See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages.

Table 2-2. F2823x Hardware Features

	FEATURE		TYPE(1)	F28235 (150 MHz)	F28234 (150 MHz)	F28232 (100 MHz)
	Instruction cycle		–	6.67 ns	6.67 ns	10 ns
	Floating-point Unit		–	No	No	No
	3.3-V on-chip flash (16-bit word)		–	256K	128K	64K
	Single-access RAM (SARAM) (16-bit		–	34K	34K	26K
	word)
	One-time programmable (OTP) ROM		–	1K	1K	1K
	(16-bit word)
	Code security for on-chip		–	Yes	Yes	Yes
	flash/SARAM/OTP blocks
	Boot ROM (8K x 16)		–	Yes	Yes	Yes
	16/32-bit External Interface (XINTF)		1	Yes	Yes	Yes
	6-channel Direct Memory Access (DMA)		0	Yes	Yes	Yes
	PWM outputs		0	ePWM1/2/3/4/5/6	ePWM1/2/3/4/5/6	ePWM1/2/3/4/5/6
	HRPWM channels		0	ePWM1A/2A/3A/4A/5A/6A	ePWM1A/2A/3A/4A/5A/6A	ePWM1A/2A/3A/4A
	32-bit Capture inputs or auxiliary PWM		0	eCAP1/2/3/4/5/6	eCAP1/2/3/4	eCAP1/2/3/4
	outputs
	32-bit QEP channels (four inputs/channel)		0	eQEP1/2	eQEP1/2	eQEP1/2
	Watchdog timer		–	Yes	Yes	Yes
		No. of channels		16	16	16
	12-Bit ADC	MSPS	2	12.5	12.5	12.5
		Conversion time		80 ns	80 ns	80 ns
	32-Bit CPU timers		–	3	3	3
	Multichannel Buffered Serial Port		1	2 (A/B)	2 (A/B)	1 (A)
	(McBSP)/SPI
	Serial Peripheral Interface (SPI)		0	1	1	1
	Serial Communications Interface (SCI)		0	3 (A/B/C)	3 (A/B/C)	2 (A/B)
	Enhanced Controller Area Network		0	2 (A/B)	2 (A/B)	2 (A/B)
	(eCAN)
	Inter-Integrated Circuit (I2C)		0	1	1	1
	General Purpose I/O pins (shared)		–	88	88	88
	External interrupts		–	8	8	8
		176-Pin PGF	–	Yes	Yes	Yes
	Packaging	176-Pin PTP	–	Yes	Yes	Yes
		179-Ball ZHH	–	Yes	Yes	Yes
		176-Ball ZJZ	–	Yes	Yes	Yes
		A: –40°C to 85°C	–	(PGF, ZHH, ZJZ)	(PGF, ZHH, ZJZ)	(PGF, ZHH, ZJZ)
	Temperature options	S: –40°C to 125°C	–	(PTP, ZJZ)	(PTP, ZJZ)	(PTP, ZJZ)
		Q: –40°C to 125°C
		(Q100	–	(PTP, ZJZ)	(PTP, ZJZ)	(PTP, ZJZ)
		Qualification)
	Product status(2)		–	TMS	TMS	TMS

(1)A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides.

(2)See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages.

14

Introduction

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TMS320F28232

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

www.ti.com

SPRS439I –JUNE 2007 –REVISED MARCH 2011

2.1Pin Assignments

The 176-pin PGF/PTP low-profile quad flatpack (LQFP) pin assignments are shown in Figure 2-1. The 179-ball ZHH ball grid array (BGA) terminal assignments are shown in Figure 2-2 through Figure 2-5. The 176-ball ZJZ plastic ball grid array (PBGA) terminal assignments are shown in Figure 2-6 through Figure 2-9.Table 2-3 describes the function(s) of each pin.

GPIO76/XD3 133

GPIO77/XD2 134

GPIO78/XD1 135

GPIO79/XD0 136

GPIO38/XWE0 137

XCLKOUT 138

VDD 139

VSS 140

GPIO28/SCIRXDA/XZCS6 141

GPIO34/ECAP1/XREADY 142

VDDIO 143

VSS 144

GPIO36/SCIRXDA/XZCS0 145

VDD 146

VSS 147

GPIO35/SCITXDA/XR/W 148 XRD 149 GPIO37/ECAP2/XZCS7 150

GPIO40/XA0/XWE1 151 GPIO41/XA1 152 GPIO42/XA2 153

VDD 154

VSS 155

GPIO43/XA3 156

GPIO44/XA4 157

GPIO45/XA5 158

VDDIO 159

VSS 160

GPIO46/XA6 161

GPIO47/XA7 162

GPIO80/XA8 163

GPIO81/XA9 164

GPIO82/XA10 165

VSS 166

VDD 167

GPIO83/XA11 168

GPIO84/XA12 169

VDDIO 170

VSS 171

GPIO85/XA13 172

GPIO86/XA14 173

GPIO87/XA15 174

GPIO39/XA16 175 GPIO31/CANTXA/XA17 176

GPIO75/XD4		GPIO74/XD5	GPIO73/XD6			GPIO72/XD7	GPIO71/XD8		GPIO70/XD9			V V GPIO69/XD10
												DD		SS
132		131	130			129	128		127			126		125		124

1 2 3 4 5 6 7 8 9
				V V				GPIO2/EPWM2A	V V
GPIO30/CANRXA/XA18 GPIO29/SCITXDA/XA19					GPIO0/EPWM1A	GPIO1/EPWM1B/ECAP6/MFSRB
				SS DD					SS DDIO

GPIO68/XD11		GPIO67/XD12		V V GPIO66/XD13						V V
				DDIO		SS				SS		DD
123		122		121		120		119		118		117

10 11 12 13 14 15 16
GPIO3/EPWM2B/ECAP5/MCLKRB
	GPIO4/EPWM3A GPIO5/EPWM3B/MFSRA/ECAP1 GPIO6/EPWM4A/EPWMSYNCI/EPWMSYNCO						V V GPIO7/EPWM4B/MCLKRA/ECAP2
							SS DD

GPIO65/XD14	GPIO64/XD15		GPIO63/SCITXDC/XD16			GPIO62/SCIRXDC/XD17		GPIO61/MFSRB/XD18		GPIO60/MCLKRB/XD19		GPIO59/MFSRA/XD20		V V V
														DD		SS		DDIO
116		115		114		113		112		111		110		109		108		107

17 18 19 20

21 22 23 24 25 26

GPIO8/EPWM5A/CANTXB/ADCSOCAO GPIO9/EPWM5B/SCITXDB/ECAP3 GPIO10/EPWM6A/CANRXB/ADCSOCBO GPIO11/EPWM6B/SCIRXDB/ECAP4

GPIO12/TZ1/CANTXB/MDXB

V V GPIO13/TZ2/CANRXB/MDRB

/XHOLD/GPIO14/TZ3SCITXDB/MCLKXB

GPIO15/TZ4/XHOLDA/SCIRXDB/MFSXB

SS DD

V XCLKIN

X1

V X2

V GPIO58/MCLKRA/XD21

GPIO57/SPISTEA/XD22 GPIO56/SPICLKA/XD23

SS

SS

DD

106 105 104 103 102 101 100

99 98

27 28 29 30 31 32 33 34 35

DD SS

DD1A18

SS1AGND SSA2 DDA2

GPIO16/SPISIMOA/CANTXB/TZ5 GPIO17/SPISOMIA/CANRXB/TZ6

V V

V

V V V ADCINA7

GPIO55/SPISOMIA/XD24 GPIO54/SPISIMOA/XD25 GPIO53/EQEP1I/XD26 GPIO52/EQEP1S/XD27 V V GPIO51/EQEP1B/XD28

GPIO50/EQEP1A/XD29 GPIO49/ECAP6/XD30

DDIO SS

97 96 95 94 93 92 91 90 89

36 37 38 39 40 41 42 43 44

ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 ADCINA0

ADCLO V

SSAIO

88 GPIO48/ECAP5/XD31

87 TCK

86 EMU1

85 EMU0

84 VDD3VFL

83 VSS

82 TEST2

81 TEST1

80 XRS

79 TMS

78 TRST

77 TDO

76 TDI

75 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO

74 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO

73 GPIO27/ECAP4/EQEP2S/MFSXB

72 GPIO26/ECAP3/EQEP2I/MCLKXB

71 VDDIO

70 VSS

69 GPIO25/ECAP2/EQEP2B/MDRB

68 GPIO24/ECAP1/EQEP2A/MDXB

67 GPIO23/EQEP1I/MFSXA/SCIRXDB

66 GPIO22/EQEP1S/MCLKXA/SCITXDB

65 GPIO21/EQEP1B/MDRA/CANRXB

64 GPIO20/EQEP1A/MDXA/CANTXB

63 GPIO19/SPISTEA/SCIRXDB/CANTXA

62 GPIO18/SPICLKA/SCITXDB/CANRXA

61 VDD

60 VSS

59 VDD2A18

58 VSS2AGND

57 ADCRESEXT

56 ADCREFP

55 ADCREFM

54 ADCREFIN

53 ADCINB7

52 ADCINB6

51 ADCINB5

50 ADCINB4

49 ADCINB3

48 ADCINB2

47 ADCINB1

46 ADCINB0

45 VDDAIO

Figure 2-1. F2833x, F2823x 176-Pin PGF/PTP LQFP (Top View)

NOTE

The powerpad on the bottom side of the PTP package is not connected to the ground (GND) of the die. Proper thermal management of the PowerPAD™ package requires PCB preparation. A thermal land is required on the surface of the PCB directly underneath the body of the PowerPAD package. The size of the thermal land should be as large as needed to dissipate the required heat. Note that the PowerPAD package with exposed pad down must be soldered to the PCB. Refer to the PowerPAD™ Thermally Enhanced Package Application Report (literature number SLMA002) for more details on using the PowerPAD package.

Copyright © 2007–2011, Texas Instruments Incorporated

Introduction

15

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TMS320F28232

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

	SPRS439I–JUNE 2007 –REVISED MARCH 2011								www.ti.com
		1	2	3	4	5	6	7
								GPIO21/
	P	VSSAIO	ADCINB0	ADCINB2	ADCINB6	ADCREFP	VSS	EQEP1B/	P
								MDRA/
								CANRXB
								GPIO22/
	N	ADCINA1	VDDAIO	ADCINB1	ADCINB5	ADCREFM	VDD	EQEP1S/	N
								MCLKXA/
								SCITXDB
								GPIO23/
	M	ADCINA2	ADCLO	ADCINA0	ADCINB4	ADCRESEXT	VDD2A18	EQEP1I/	M
								MFSXA/
								SCIRXDB
							GPIO18/	GPIO20/
	L	ADCINA5	ADCINA4	ADCINA3	ADCINB3	ADCREFIN	SPICLKA/	EQEP1A/	L
							SCITXDB/	MDXA/
							CANRXA	CANTXB
								GPIO19/
	K	VSS1AGND	VDDA2	VSSA2	ADCINA7	ADCINB7	VSS2AGND	SPISTEA/	K
								SCIRXDB/
								CANTXA
		GPIO17/					6	7
	J	SPISOMIA/	VDD	VSS	VDD1A18	ADCINA6	J
		CANRXB/
		TZ6
			GPIO14/	GPIO13/	GPIO15/	GPIO16/
	H	VDD	TZ3 XHOLD/	TZ2/	TZ4 XHOLDA/	SPISIMOA/	H
			SCITXDB/	CANRXB/	SCIRXDB/	CANTXB/
			MCLKXB	MDRB	MFSXB	TZ5
		1	2	3	4	5

Figure 2-2. F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Upper Left Quadrant) (Bottom View)

16

Introduction

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TMS320F28232

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

www.ti.com SPRS439I –JUNE 2007 –REVISED MARCH 2011

		8	9	10	11	12	13	14
			GPIO33/				GPIO48/	GPIO50/
			SCLA/
	P	VSS		TMS	TEST2	EMU1	ECAP5/	EQEP1A/	P
			EPWMSYNCO/
							XD31	XD29
			ADCSOCBO
		GPIO25/	GPIO32/				GPIO49/
		ECAP2/	SDAA/
	N			VSS	VSS	TCK	ECAP6/	VDDIO	N
		EQEP2B/	EPWMSYNCI/
							XD30
		MDRB	ADCSOCAO
		GPIO24/					GPIO51/	GPIO52/
		ECAP1/
	M		TDI	TRST	VDD3VFL	VSS	EQEP1B/	EQEP1S/	M
		EQEP2A/
							XD28	XD27
		MDXB
			GPIO27/			GPIO53/	GPIO54/	GPIO55/
			ECAP4/
	L	VDDIO		XRS	EMU0	EQEP1I/	SPISIMOA/	SPISOMIA/	L
			EQEP2S/
						XD26	XD25	XD24
			MFSXB
		GPIO26/			GPIO56/	GPIO58/	GPIO57/
		ECAP3/
	K		TDO	TEST1	SPICLKA/	MCLKRA/	SPISTEA/	VDD	K
		EQEP2I/
					XD23	XD21	XD22
		MCLKXB
		8	9
			J	VSS	X2	VSS	X1	XCLKIN	J
								GPIO59/
			H	VSS	VDDIO	VDD	VSS	MFSRA/	H
								XD20
				10	11	12	13	14

Figure 2-3. F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Upper Right Quadrant) (Bottom View)

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Introduction

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TMS320F28232

	TMS320F28335, TMS320F28334, TMS320F28332
	TMS320F28235, TMS320F28234, TMS320F28232
	SPRS439I–JUNE 2007 –REVISED MARCH 2011								www.ti.com
		1	2	3	4	5
			GPIO11/	GPIO12/	GPIO10/	GPIO9/
	G	VSS	EPWM6B/	TZ1/	EPWM6A/	EPWM5B/	G
			SCIRXDB/	CANTXB/	CANRXB/	SCITXDB/
			ECAP4	MDXB	ADCSOCBO	ECAP3
		GPIO8/	GPIO7/
	F	EPWM5A/	EPWM4B/	VDD	VSS	VDDIO	F
		CANTXB/	MCLKRA/
		ADCSOCAO	ECAP2				6	7
		GPIO6/		GPIO5/	GPIO3/
	E	EPWM4A/	GPIO4/	EPWM3B/	EPWM2B/	GPIO84/	GPIO81/	VDDIO	E
		EPWMSYNCI/	EPWM3A	MFSRA/	ECAP5/	XA12	XA9
		EPWMSYNCO		ECAP1	MCLKRB
				GPIO1/
	D	VSS	GPIO2/	EPWM1B/	GPIO86/	GPIO83/	VSS	GPIO45/	D
			EPWM2A	ECAP6/	XA14	XA11		XA5
				MFSRB
		GPIO0/	GPIO29/		GPIO85/	GPIO82/	GPIO80/
	C		SCITXDA/	VSS				VSS	C
		EPWM1A			XA13	XA10	XA8
			XA19
			GPIO30/	GPIO39/			GPIO46/	GPIO43/
	B	VDD	CANRXA/		VSS	VDD			B
				XA16			XA6	XA3
			XA18
			GPIO31/	GPIO87/			GPIO47/	GPIO44/
	A		CANTXA/		VDDIO	VSS			A
				XA15			XA7	XA4
			XA17
		1	2	3	4	5	6	7
	Figure 2-4. F2833x, F2823x 179-Ball ZHH MicroStar BGA™ (Lower Left Quadrant) (Bottom View)

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TMS320F28235, TMS320F28234, TMS320F28232

www.ti.com		SPRS439I –JUNE 2007 –REVISED MARCH 2011

				10	11	12	13	14
				GPIO64/	GPIO63/	GPIO61/	GPIO62/	GPIO60/
			G		SCITXDC/	MFSRB/	SCIRXDC	MCLKRB/	G
				XD15
					XD16	XD18	XD17	XD19
			F	GPIO69/	GPIO66/	VSS	VDD	GPIO65/	F
				XD10	XD13			XD14
		8	9
				GPIO28/	GPIO68/		GPIO67/
	E	VSS	VDD	SCIRXDA/		VDDIO		VSS	E
					XD11		XD12
				XZCS6
		GPIO40/	GPIO37/	GPIO34/	GPIO38/	GPIO70/
	D	XA0/	ECAP2/	ECAP1/			VDD	VSS	D
					XWE0	XD9
		XWE1	XZCS7	XREADY
				GPIO36/		GPIO73/	GPIO74/	GPIO71/
	C	VDD	VSS	SCIRXDA/	XCLKOUT				C
						XD6	XD5	XD8
				XZCS0
	B	GPIO42/	XRD	VDDIO	VDD	GPIO78/	GPIO76/	GPIO72/	B
		XA2				XD1	XD3	XD7
		GPIO41/	GPIO35/			GPIO79/	GPIO77/	GPIO75/
	A		SCITXDA/	VSS	VSS				A
		XA1				XD0	XD2	XD4
			XR/W
		8	9	10	11	12	13	14

Figure 2-5. F2833x, F2823x 179-Ball ZHH MicroStar BGA ™ (Lower Right Quadrant) (Bottom View)

Copyright © 2007–2011, Texas Instruments Incorporated

Introduction

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TMS320F28232

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011

www.ti.com

1

2

3

4

5

6

7

P

VSSA2

VSS2AGND

ADCINB0

ADCREFM

ADCREFP

ADCRESEXT

ADCREFIN

N

VSSAIO

ADCLO

ADCINB1

ADCINB3

ADCINB5

ADCINB7

EMU0

M

ADCINA2

ADCINA1

ADCINA0

ADCINB2

ADCINB4

ADCINB6

TEST1

L

ADCINA5

ADCINA4

ADCINA3

VSS1AGND

VDDAIO

VDD2A18

TEST2

K

ADCINA7

ADCINA6

VDD1A18

VDDA2

GPIO15/

GPIO16/

GPIO17/

J

TZ4/XHOLDA/

SPISIMOA/

SPISOMIA/

VDD

VSS

VSS

SCIRXDB/

CANTXB/

CANRXB/

MFSXB

TZ5

TZ6

GPIO12/

GPIO13/

GPIO14/

H

TZ1/

TZ2/

TZ3 XHOLD/

VDD

VSS

VSS

CANTXB/

CANRXB/

SCITXDB/

MDXB

MDRB

MCLKXB

Figure 2-6. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Left Quadrant) (Bottom View)

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TMS320F28232

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TMS320F28235, TMS320F28234, TMS320F28232

www.ti.com SPRS439I –JUNE 2007 –REVISED MARCH 2011

	8	9	10	11	12	13	14
		GPIO20/	GPIO23/	GPIO26/	GPIO33/
	EMU1	EQEP1A/	EQEP1I/	ECAP3/	SCLA/	VSS	VSS	P
		MDXA/	MFSXA/	EQEP2I/	EPWMSYNCO/
		CANTXB	SCIRXDB	MCLKXB	ADCSOCBO
	GPIO18/	GPIO21/	GPIO24/	GPIO27/
	SPICLKA/	EQEP1B/	ECAP1/	ECAP4/	TDI	TDO	VDDIO	N
	SCITXDB/	MDRA/	EQEP2A/	EQEP2S/
	CANRXA	CANRXB	MDXB	MFSXB
	GPIO19/	GPIO22/	GPIO25/	GPIO32/
	SPISTEA/	EQEP1S/	ECAP2/	SDAA/	TMS	XRS	TCK	M
	SCIRXDB/	MCLKXA/	EQEP2B/	EPWMSYNCI/
	CANTXA	SCITXDB	MDRB	ADSOCAO
					GPIO50/	GPIO49/	GPIO48/
	VDD	VDD3VFL	VDDIO	TRST	EQEP1A/	ECAP6/	ECAP5/	L
					XD29	XD30	XD31
					GPIO53	GPIO52/	GPIO51/
				VDD	EQEP1I/	EQEP1S/	EQEP1B/	K
					XD26	XD27	XD28
					GPIO56/	GPIO55/	GPIO54/
	VSS	VSS		VDD	SPICLKA/	SPISOMIA/	SPISIMOA/	J
					XD23	XD24	XD25
				GPIO59/	GPIO58/	GPIO57/
	VSS	VSS		MFSRA/	MCLKRA/	SPISTEA/	X2	H
				XD20	XD21	XD22

Figure 2-7. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Upper Right Quadrant) (Bottom View)

Copyright © 2007–2011, Texas Instruments Incorporated

Introduction

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TMS320F28232

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011

www.ti.com

	GPIO9/		GPIO10/			GPIO11/
G	EPWM5B/		EPWM6A/			EPWM6B/		VDDIO		VSS	VSS
	SCITXDB/		CANRXB/			SCIRXDB/
	ECAP3
		ADCSOCBO				ECAP4
	GPIO6/		GPIO7/			GPIO8/
F	EPWM4A/		EPWM4B/			EPWM5A/		VDD		VSS	VSS
	EPWMSYNCI/		MCLKRA/			CANTXB/
	EPWMSYNCO		ECAP2			ADCSOCAO
	GPIO3/					GPIO5/
E	EPWM2B/		GPIO4/			EPWM3B/		VDDIO
	ECAP5/		EPWM3A			MFSRA/
	MCLKRB					ECAP1
			GPIO1/
D	GPIO0/		EPWM1B/			GPIO2/		VDD	VDD	GPIO47/	VDDIO
	EPWM1A		ECAP6/			EPWM2A				XA7
			MFSRB
	GPIO29/		GPIO30/			GPIO39/		GPIO85/	GPIO82/	GPIO46/	GPIO43/
C	SCITXDA/		CANRXA/
						XA16		XA13	XA10	XA6	XA3
	XA19		XA18
			GPIO31/			GPIO87/		GPIO84/	GPIO81/	GPIO45/	GPIO42/
B	VDDIO		CANTXA/
						XA15		XA12	XA9	XA5	XA2
			XA17
A	VSS		VSS			GPIO86/		GPIO83/	GPIO80/	GPIO44/	GPIO41/
						XA14		XA11	XA8	XA4	XA1
	1	2			3			4	5	6	7

Figure 2-8. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Left Quadrant) (Bottom View)

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TMS320F28232

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

www.ti.com			SPRS439I –JUNE 2007 –REVISED MARCH 2011

GPIO60/

VSS

VSS

VDDIO

MCLKRB/

XCLKIN

X1

G

XD19

GPIO63/

GPIO62/

GPIO61/

VSS

VSS

VDD

SCITXDC/

SCIRXDC/

MFSRB/

F

XD16

XD17

XD18

VDD

GPIO66/

GPIO65/

GPIO64/

E

XD13

XD14

XD15

GPIO28/

GPIO69/

GPIO68/

GPIO67/

VDD

VDD

SCIRXDA/

VDDIO

D

XD10

XD11

XD12

XZCS6

GPIO40/

GPIO36/

GPIO38/

GPIO78/

GPIO75/

GPIO71/

GPIO70/

SCIRXDA/

C

XD8

XD9

XA0/XWE1

XWE0

XD1

XD4

XZCS0

GPIO37/

GPIO35/

GPIO79/

GPIO77/

GPIO74/

GPIO72

ECAP2/

SCITXDA/

VSS

B

XD0

XD2

XD5

XD7

XZCS7

XR/W

GPIO34/

GPIO76/

GPIO73/

ECAP1/

XCLKOUT

VDDIO

VSS

A

XRD

XD3

XD6

XREADY

8

9

10

11

12

13

14

Figure 2-9. F2833x, F2823x 176-Ball ZJZ Plastic BGA (Lower Right Quadrant) (Bottom View)

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Introduction

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TMS320F28232

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TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011

www.ti.com

2.2Signal Descriptions

Table 2-3 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 and Table 2-2 for details. Inputs are not 5-V tolerant. All pins capable of producing an XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin is not configured for XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unless otherwise indicated). All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0–GPIO11 pins are not enabled at reset. The pullups on GPIO12–GPIO87 are enabled upon reset.

Table 2-3. Signal Descriptions

PIN NO.

NAME

PGF/

ZHH

ZJZ

DESCRIPTION

(1)

PTP

BALL #

BALL #

PIN #

JTAG

JTAG test reset with internal pulldown.

TRST,

when driven high, gives the scan system

control of the operations of the device. If this signal is not connected or driven low, the

device operates in its functional mode, and the test reset signals are ignored.

NOTE: TRST is an active high test pin and must be maintained low at all times during

TRST

78

M10

L11

normal device operation. An external pulldown resistor is required on this pin. The value of

this resistor should be based on drive strength of the debugger pods applicable to the

design. A 2.2-kΩ resistor generally offers adequate protection. Since this is

application-specific, it is recommended that each target board be validated for proper

operation of the debugger and the application. (I, ↓)

TCK

87

N12

M14

JTAG test clock with internal pullup (I, ↑)

TMS

79

P10

M12

JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into

the TAP controller on the rising edge of TCK. (I, ↑)

TDI

76

M9

N12

JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register

(instruction or data) on a rising edge of TCK. (I, ↑)

TDO

77

K9

N13

JTAG scan out, test data output (TDO). The contents of the selected register (instruction or

data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)

Emulator pin 0. When

is driven high, this pin is used as an interrupt to or from the

TRST

emulator system and is defined as input/output through the JTAG scan. This pin is also

used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state

and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the

EMU0

85

L11

N7

device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)

NOTE: An external pullup resistor is required on this pin. The value of this resistor should

be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to

4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended

that each target board be validated for proper operation of the debugger and the

application.

Emulator pin 1. When

is driven high, this pin is used as an interrupt to or from the

TRST

emulator system and is defined as input/output through the JTAG scan. This pin is also

used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state

and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the

EMU1

86

P12

P8

device into boundary-scan mode. (I/O/Z, 8 mA drive ↑)

NOTE: An external pullup resistor is required on this pin. The value of this resistor should

be based on the drive strength of the debugger pods applicable to the design. A 2.2-kΩ to

4.7-kΩ resistor is generally adequate. Since this is application-specific, it is recommended

that each target board be validated for proper operation of the debugger and the

application.

FLASH

VDD3VFL

84

M11

L9

3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.

TEST1

81

K10

M7

Test Pin. Reserved for TI. Must be left unconnected. (I/O)

TEST2

82

P11

L7

Test Pin. Reserved for TI. Must be left unconnected. (I/O)

(1)I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown

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	TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com	SPRS439I –JUNE 2007 –REVISED MARCH 2011

Table 2-3. Signal Descriptions (continued)

				PIN NO.
		NAME	PGF/	ZHH		ZJZ			DESCRIPTION	(1)
			PTP
				BALL #		BALL #
			PIN #
								CLOCK
							Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half
							the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 18:16
	XCLKOUT		138	C11		A10	(XTIMCLK) and bit 2 (CLKMODE) in the XINTCNF2 register. At reset, XCLKOUT =
							SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XINTCNF2[CLKOFF]
							to 1. Unlike other GPIO pins, the XCLKOUT pin is not placed in high-impedance state
							during a reset. (O/Z, 8 mA drive).
							External Oscillator Input. This pin is to feed a clock from an external 3.3-V oscillator. In this
	XCLKIN		105	J14		G13	case, the X1 pin must be tied to GND. If a crystal/resonator is used (or if an external 1.9-V
							oscillator is used to feed clock to X1 pin), this pin must be tied to GND. (I)
							Internal/External Oscillator Input. To use the internal oscillator, a quartz crystal or a
							ceramic resonator may be connected across X1 and X2. The X1 pin is referenced to the
	X1		104	J13		G14	1.9-V core digital power supply. A 1.9-V external oscillator may be connected to the X1 pin.
							In this case, the XCLKIN pin must be connected to ground. If a 3.3-V external oscillator is
							used with the XCLKIN pin, X1 must be tied to GND. (I)
	X2		102	J11		H14	Internal Oscillator Output. A quartz crystal or a ceramic resonator may be connected
							across X1 and X2. If X2 is not used, it must be left unconnected. (O)
								RESET
							Device Reset (in) and Watchdog Reset (out).
							Device reset.	XRS	causes the device to terminate execution. The PC will point to the
							address contained at the location 0x3FFFC0. When XRS is brought to a high level,
							execution begins at the location pointed to by the PC. This pin is driven low by the DSC
	XRS		80	L10		M13
							when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the
							watchdog reset duration of 512 OSCCLK cycles. (I/OD, ↑)
							The output buffer of this pin is an open-drain with an internal pullup. It is recommended
							that this pin be driven by an open-drain device.
							ADC SIGNALS
	ADCINA7		35	K4		K1	ADC Group A, Channel 7 input (I)
	ADCINA6		36	J5		K2	ADC Group A, Channel 6 input (I)
	ADCINA5		37	L1		L1	ADC Group A, Channel 5 input (I)
	ADCINA4		38	L2		L2	ADC Group A, Channel 4 input (I)
	ADCINA3		39	L3		L3	ADC Group A, Channel 3 input (I)
	ADCINA2		40	M1		M1	ADC Group A, Channel 2 input (I)
	ADCINA1		41	N1		M2	ADC Group A, Channel 1 input (I)
	ADCINA0		42	M3		M3	ADC Group A, Channel 0 input (I)
	ADCINB7		53	K5		N6	ADC Group B, Channel 7 input (I)
	ADCINB6		52	P4		M6	ADC Group B, Channel 6 input (I)
	ADCINB5		51	N4		N5	ADC Group B, Channel 5 input (I)
	ADCINB4		50	M4		M5	ADC Group B, Channel 4 input (I)
	ADCINB3		49	L4		N4	ADC Group B, Channel 3 input (I)
	ADCINB2		48	P3		M4	ADC Group B, Channel 2 input (I)
	ADCINB1		47	N3		N3	ADC Group B, Channel 1 input (I)
	ADCINB0		46	P2		P3	ADC Group B, Channel 0 input (I)
	ADCLO		43	M2		N2	Low Reference (connect to analog ground) (I)
	ADCRESEXT		57	M5		P6	ADC External Current Bias Resistor. Connect a 22-kΩ resistor to analog ground.
	ADCREFIN		54	L5		P7	External reference input (I)

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SPRS439I–JUNE 2007 –REVISED MARCH 2011 www.ti.com

Table 2-3. Signal Descriptions (continued)

		PIN NO.
NAME	PGF/	ZHH		ZJZ	DESCRIPTION	(1)
	PTP
		BALL #		BALL #
	PIN #
					Internal Reference Positive Output. Requires a low ESR (under 1.5 Ω) ceramic bypass
ADCREFP	56	P5		P5	capacitor of 2.2 μF to analog ground. (O)
					NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data
					sheet that is used in the system.
					Internal Reference Medium Output. Requires a low ESR (under 1.5 Ω) ceramic bypass
ADCREFM	55	N5		P4	capacitor of 2.2 μF to analog ground. (O)
					NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data
					sheet that is used in the system.
					CPU AND I/O POWER PINS
VDDA2	34	K2		K4	ADC Analog Power Pin
VSSA2	33	K3		P1	ADC Analog Ground Pin
VDDAIO	45	N2		L5	ADC Analog I/O Power Pin
VSSAIO	44	P1		N1	ADC Analog I/O Ground Pin
VDD1A18	31	J4		K3	ADC Analog Power Pin
VSS1AGND	32	K1		L4	ADC Analog Ground Pin
VDD2A18	59	M6		L6	ADC Analog Power Pin
VSS2AGND	58	K6		P2	ADC Analog Ground Pin
VDD	4	B1		D4
VDD	15	B5		D5
VDD	23	B11		D8
VDD	29	C8		D9
VDD	61	D13		E11
VDD	101	E9		F4
VDD	109	F3		F11	CPU and Logic Digital Power Pins
VDD	117	F13		H4
VDD	126	H1		J4
VDD	139	H12		J11
VDD	146	J2		K11
VDD	154	K14		L8
VDD	167	N6
VDDIO	9	A4		A13
VDDIO	71	B10		B1
VDDIO	93	E7		D7
VDDIO	107	E12		D11
VDDIO	121	F5		E4	Digital I/O Power Pin
VDDIO	143	L8		G4
VDDIO	159	H11		G11
VDDIO	170	N14		L10
VDDIO				N14

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TMS320F28232

						TMS320F28335, TMS320F28334, TMS320F28332
						TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com						SPRS439I –JUNE 2007 –REVISED MARCH 2011
					Table 2-3. Signal Descriptions (continued)
			PIN NO.
NAME		PGF/	ZHH		ZJZ	DESCRIPTION	(1)
		PTP
			BALL #		BALL #
		PIN #
VSS		3	A5		A1
VSS		8	A10		A2
VSS		14	A11		A14
VSS		22	B4		B14
VSS		30	C3		F6
VSS		60	C7		F7
VSS		70	C9		F8
VSS		83	D1		F9
VSS		92	D6		G6
VSS		103	D14		G7
VSS		106	E8		G8
VSS		108	E14		G9
VSS		118	F4		H6	Digital Ground Pins
VSS		120	F12		H7
VSS		125	G1		H8
VSS		140	H10		H9
VSS		144	H13		J6
VSS		147	J3		J7
VSS		155	J10		J8
VSS		160	J12		J9
VSS		166	M12		P13
VSS		171	N10		P14
VSS			N11
VSS			P6
VSS			P8
						GPIO AND PERIPHERAL SIGNALS
GPIO0						General purpose input/output 0 (I/O/Z)
EPWM1A		5	C1		D1	Enhanced PWM1 Output A and HRPWM channel (O)
-						-
-						-
GPIO1						General purpose input/output 1 (I/O/Z)
EPWM1B		6	D3		D2	Enhanced PWM1 Output B (O)
ECAP6						Enhanced Capture 6 input/output (I/O)
MFSRB						McBSP-B receive frame synch (I/O)
GPIO2						General purpose input/output 2 (I/O/Z)
EPWM2A		7	D2		D3	Enhanced PWM2 Output A and HRPWM channel (O)
-						-
-						-
GPIO3						General purpose input/output 3 (I/O/Z)
EPWM2B		10	E4		E1	Enhanced PWM2 Output B (O)
ECAP5						Enhanced Capture 5 input/output (I/O)
MCLKRB						McBSP-B receive clock (I/O)
GPIO4						General purpose input/output 4 (I/O/Z)
EPWM3A		11	E2		E2	Enhanced PWM3 output A and HRPWM channel (O)
-						-
-						-
GPIO5						General purpose input/output 5 (I/O/Z)
EPWM3B		12	E3		E3	Enhanced PWM3 output B (O)
MFSRA						McBSP-A receive frame synch (I/O)
ECAP1						Enhanced Capture input/output 1 (I/O)
Copyright ©	2007–2011, Texas Instruments Incorporated							Introduction	27

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TMS320F28232

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011 www.ti.com

Table 2-3. Signal Descriptions (continued)

PIN NO.

NAME

PGF/

ZHH

ZJZ

DESCRIPTION

(1)

PTP

BALL #

BALL #

PIN #

GPIO6

General purpose input/output 6 (I/O/Z)

EPWM4A

13

E1

F1

Enhanced PWM4 output A and HRPWM channel (O)

EPWMSYNCI

External ePWM sync pulse input (I)

EPWMSYNCO

External ePWM sync pulse output (O)

GPIO7

General purpose input/output 7 (I/O/Z)

EPWM4B

16

F2

F2

Enhanced PWM4 output B (O)

MCLKRA

McBSP-A receive clock (I/O)

ECAP2

Enhanced capture input/output 2 (I/O)

GPIO8

General Purpose Input/Output 8 (I/O/Z)

EPWM5A

17

F1

F3

Enhanced PWM5 output A and HRPWM channel (O)

CANTXB

Enhanced CAN-B transmit (O)

ADCSOCAO

ADC start-of-conversion A (O)

GPIO9

General purpose input/output 9 (I/O/Z)

EPWM5B

18

G5

G1

Enhanced PWM5 output B (O)

SCITXDB

SCI-B transmit data(O)

ECAP3

Enhanced capture input/output 3 (I/O)

GPIO10

General purpose input/output 10 (I/O/Z)

EPWM6A

19

G4

G2

Enhanced PWM6 output A and HRPWM channel (O)

CANRXB

Enhanced CAN-B receive (I)

ADCSOCBO

ADC start-of-conversion B (O)

GPIO11

General purpose input/output 11 (I/O/Z)

EPWM6B

20

G2

G3

Enhanced PWM6 output B (O)

SCIRXDB

SCI-B receive data (I)

ECAP4

Enhanced CAP Input/Output 4 (I/O)

GPIO12

General purpose input/output 12 (I/O/Z)

TZ1

21

G3

H1

Trip Zone input 1 (I)

CANTXB

Enhanced CAN-B transmit (O)

MDXB

McBSP-B transmit serial data (O)

GPIO13

General purpose input/output 13 (I/O/Z)

TZ2

24

H3

H2

Trip Zone input 2 (I)

CANRXB

Enhanced CAN-B receive (I)

MDRB

McBSP-B receive serial data (I)

GPIO14

General purpose input/output 14 (I/O/Z)

Trip Zone input 3/External Hold Request.

when active (low), requests the external

XHOLD,

interface (XINTF) to release the external bus and place all buses and strobes into a

high-impedance state. To prevent this from happening when TZ3 signal goes active,

TZ3/XHOLD

25

H2

H3

disable this function by writing XINTCNF2[HOLD] = 1. If this is not done, the XINTF bus

will go into high impedance anytime TZ3 goes low. On the ePWM side, TZn signals are

ignored by default, unless they are enabled by the code. The XINTF will release the bus

when any current access is complete and there are no pending accesses on the XINTF. (I)

SCITXDB

SCI-B Transmit (O)

MCLKXB

McBSP-B transmit clock (I/O)

GPIO15

General purpose input/output 15 (I/O/Z)

Trip Zone input 4/External Hold Acknowledge. The pin function for this option is based on

the direction chosen in the GPADIR register. If the pin is configured as an input, then

TZ4

function is chosen. If the pin is configured as an output, then XHOLDA function is chosen.

TZ4/XHOLDA

26

H4

J1

XHOLDA is driven active (low) when the XINTF has granted an XHOLD request. All XINTF

buses and strobe signals will be in a high-impedance state. XHOLDA is released when the

XHOLD signal is released. External devices should only drive the external bus when

XHOLDA is active (low). (I/O)

SCIRXDB

SCI-B receive (I)

MFSXB

McBSP-B transmit frame synch (I/O)

GPIO16

General purpose input/output 16 (I/O/Z)

SPISIMOA

27

H5

J2

SPI slave in, master out (I/O)

CANTXB

Enhanced CAN-B transmit (O)

TZ5

Trip Zone input 5 (I)

28

Introduction

Copyright © 2007–2011, Texas Instruments Incorporated

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TMS320F28232

	TMS320F28335, TMS320F28334, TMS320F28332
	TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com	SPRS439I –JUNE 2007 –REVISED MARCH 2011

Table 2-3. Signal Descriptions (continued)

				PIN NO.
	NAME		PGF/	ZHH		ZJZ	DESCRIPTION	(1)
			PTP
				BALL #		BALL #
			PIN #
	GPIO17						General purpose input/output 17 (I/O/Z)
	SPISOMIA		28	J1		J3	SPI-A slave out, master in (I/O)
	CANRXB						Enhanced CAN-B receive (I)
	TZ6						Trip zone input 6 (I)
	GPIO18						General purpose input/output 18 (I/O/Z)
	SPICLKA		62	L6		N8	SPI-A clock input/output (I/O)
	SCITXDB						SCI-B transmit (O)
	CANRXA						Enhanced CAN-A receive (I)
	GPIO19						General purpose input/output 19 (I/O/Z)
	SPISTEA		63	K7		M8	SPI-A slave transmit enable input/output (I/O)
	SCIRXDB						SCI-B receive (I)
	CANTXA						Enhanced CAN-A transmit (O)
	GPIO20						General purpose input/output 20 (I/O/Z)
	EQEP1A		64	L7		P9	Enhanced QEP1 input A (I)
	MDXA						McBSP-A transmit serial data (O)
	CANTXB						Enhanced CAN-B transmit (O)
	GPIO21						General purpose input/output 21 (I/O/Z)
	EQEP1B		65	P7		N9	Enhanced QEP1 input B (I)
	MDRA						McBSP-A receive serial data (I)
	CANRXB						Enhanced CAN-B receive (I)
	GPIO22						General purpose input/output 22 (I/O/Z)
	EQEP1S		66	N7		M9	Enhanced QEP1 strobe (I/O)
	MCLKXA						McBSP-A transmit clock (I/O)
	SCITXDB						SCI-B transmit (O)
	GPIO23						General purpose input/output 23 (I/O/Z)
	EQEP1I		67	M7		P10	Enhanced QEP1 index (I/O)
	MFSXA						McBSP-A transmit frame synch (I/O)
	SCIRXDB						SCI-B receive (I)
	GPIO24						General purpose input/output 24 (I/O/Z)
	ECAP1		68	M8		N10	Enhanced capture 1 (I/O)
	EQEP2A						Enhanced QEP2 input A (I)
	MDXB						McBSP-B transmit serial data (O)
	GPIO25						General purpose input/output 25 (I/O/Z)
	ECAP2		69	N8		M10	Enhanced capture 2 (I/O)
	EQEP2B						Enhanced QEP2 input B (I)
	MDRB						McBSP-B receive serial data (I)
	GPIO26						General purpose input/output 26 (I/O/Z)
	ECAP3		72	K8		P11	Enhanced capture 3 (I/O)
	EQEP2I						Enhanced QEP2 index (I/O)
	MCLKXB						McBSP-B transmit clock (I/O)
	GPIO27						General purpose input/output 27 (I/O/Z)
	ECAP4		73	L9		N11	Enhanced capture 4 (I/O)
	EQEP2S						Enhanced QEP2 strobe (I/O)
	MFSXB						McBSP-B transmit frame synch (I/O)
	GPIO28						General purpose input/output 28 (I/O/Z)
	SCIRXDA		141	E10		D10	SCI receive data (I)
	XZCS6						External Interface zone 6 chip select (O)
	GPIO29						General purpose input/output 29. (I/O/Z)
	SCITXDA		2	C2		C1	SCI transmit data (O)
	XA19						External Interface Address Line 19 (O)
	GPIO30						General purpose input/output 30 (I/O/Z)
	CANRXA		1	B2		C2	Enhanced CAN-A receive (I)
	XA18						External Interface Address Line 18 (O)
	GPIO31						General purpose input/output 31 (I/O/Z)
	CANTXA		176	A2		B2	Enhanced CAN-A transmit (O)
	XA17						External Interface Address Line 17 (O)

Copyright © 2007–2011, Texas Instruments Incorporated

Introduction

29

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TMS320F28232

TMS320F28335, TMS320F28334, TMS320F28332

TMS320F28235, TMS320F28234, TMS320F28232

SPRS439I–JUNE 2007 –REVISED MARCH 2011 www.ti.com

Table 2-3. Signal Descriptions (continued)

							PIN NO.
		NAME				PGF/	ZHH		ZJZ	DESCRIPTION	(1)
						PTP
							BALL #		BALL #
						PIN #
	GPIO32									General purpose input/output 32 (I/O/Z)
	SDAA					74	N9		M11	I2C data open-drain bidirectional port (I/OD)
	EPWMSYNCI									Enhanced PWM external sync pulse input (I)
	ADCSOCAO									ADC start-of-conversion A (O)
	GPIO33									General-Purpose Input/Output 33 (I/O/Z)
	SCLA					75	P9		P12	I2C clock open-drain bidirectional port (I/OD)
	EPWMSYNCO									Enhanced PWM external synch pulse output (O)
	ADCSOCBO									ADC start-of-conversion B (O)
										General-Purpose Input/Output 34 (I/O/Z)
	GPIO34									Enhanced Capture input/output 1 (I/O)
	ECAP1					142	D10		A9	External Interface Ready signal. Note that this pin is always (directly) connected to the
	XREADY									XINTF. If an application uses this pin as a GPIO while also using the XINTF, it should
										configure the XINTF to ignore READY.
	GPIO35									General-Purpose Input/Output 35 (I/O/Z)
	SCITXDA					148	A9		B9	SCI-A transmit data (O)
	XR/W									External Interface read, not write strobe
	GPIO36									General-Purpose Input/Output 36 (I/O/Z)
	SCIRXDA					145	C10		C9	SCI receive data (I)
	XZCS0									External Interface zone 0 chip select (O)
	GPIO37									General-Purpose Input/Output 37 (I/O/Z)
	ECAP2					150	D9		B8	Enhanced Capture input/output 2 (I/O)
	XZCS7									External Interface zone 7 chip select (O)
	GPIO38									General-Purpose Input/Output 38 (I/O/Z)
-						137	D11		C10	-
	XWE0									External Interface Write Enable 0 (O)
	GPIO39									General-Purpose Input/Output 39 (I/O/Z)
-						175	B3		C3	-
	XA16									External Interface Address Line 16 (O)
	GPIO40									General-Purpose Input/Output 40 (I/O/Z)
-						151	D8		C8	-
	XA0/XWE1									External Interface Address Line 0/External Interface Write Enable 1 (O)
	GPIO41									General-Purpose Input/Output 41 (I/O/Z)
-						152	A8		A7	-
	XA1									External Interface Address Line 1 (O)
	GPIO42									General-Purpose Input/Output 42 (I/O/Z)
-						153	B8		B7	-
	XA2									External Interface Address Line 2 (O)
	GPIO43									General-Purpose Input/Output 43 (I/O/Z)
-						156	B7		C7	-
	XA3									External Interface Address Line 3 (O)
	GPIO44									General-Purpose Input/Output 44 (I/O/Z)
-						157	A7		A6	-
	XA4									External Interface Address Line 4 (O)
	GPIO45									General-Purpose Input/Output 45 (I/O/Z)
-						158	D7		B6	-
	XA5									External Interface Address Line 5 (O)
	GPIO46									General-Purpose Input/Output 46 (I/O/Z)
-						161	B6		C6	-
	XA6									External Interface Address Line 6 (O)
	GPIO47									General-Purpose Input/Output 47 (I/O/Z)
-						162	A6		D6	-
	XA7									External Interface Address Line 7 (O)
	GPIO48									General-Purpose Input/Output 48 (I/O/Z)
	ECAP5					88	P13		L14	Enhanced Capture input/output 5 (I/O)
	XD31									External Interface Data Line 31 (I/O/Z)
	GPIO49									General-Purpose Input/Output 49 (I/O/Z)
	ECAP6					89	N13		L13	Enhanced Capture input/output 6 (I/O)
	XD30									External Interface Data Line 30 (I/O/Z)
30				Introduction						Copyright © 2007–2011, Texas Instruments Incorporated

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