Texas Instruments TLV5623IDR, TLV5623IDGKR, TLV5623ID, TLV5623IDGK, TLV5623CDR Datasheet

TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS231 ± JUNE 1999

D8-Bit Voltage Output DAC

DProgrammable Settling Time vs Power

Consumption

3 μs in Fast Mode

9 μs in Slow Mode

DUltra Low Power Consumption:

900 μW Typ in Slow Mode at 3 V

2.1 mW Typ in Fast Mode at 3 V

DDifferential Nonlinearity . . . <0.2 LSB Typ

DCompatible With TMS320 and SPI Serial Ports

DPower-Down Mode

description

DBuffered High-Impedance Reference Input

DMonotonic Over Temperature

DAvailable in MSOP Package

applications

DDigital Servo Control Loops

DDigital Offset and Gain Adjustment

DIndustrial Process Control

DMachine and Motion Control Devices

DMass Storage Devices

D OR DGK PACKAGE

(TOP VIEW)

The TLV5623 is a 8-bit voltage output digital-to-	DIN						VDD
					1	8
analog converter (DAC) with a flexible 4-wire
serial interface. The 4-wire serial interface allows	SCLK				2	7	OUT
glueless interface to TMS320, SPI, QSPI, and		CS			3	6	REFIN
Microwire serial ports. The TLV5623 is pro-		FS			4	5	AGND
grammed with a 16-bit serial string containing 4
control and 12 data bits. Developed for a wide
range of supply voltages, the TLV5623 can
operate from 2.7 V to 5.5 V.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need for a low source impedance drive to the terminal.

Implemented with a CMOS process, the TLV5623 is designed for single supply operation from 2.7 V to 5.5 V. The device is available in an 8-terminal SOIC package. The TLV5623C is characterized for operation from 0°C to 70°C. The TLV5623I is characterized for operation from ±40°C to 85°C.

AVAILABLE OPTIONS

	PACKAGE
TA	SMALL OUTLINE²		MSOP
	(D)		(DGK)
0°C to 70°C	TLV5623CD		TLV5623CDGK
± 40°C to 85°C	TLV5623ID		TLV5623IDGK

² Available in tape and reel as the TLV5623CDR and the TLV5623IDR

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1999, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS231 ± JUNE 1999

functional block diagram

	_
6	+
REFIN
1	Serial Input	10	8
DIN	Register		8-Bit	8		7
			Data		x2
2			Latch			OUT
SCLK	16 Cycle	Update
3
CS	Timer
4
FS
	Power-On		2
	Reset		Speed/Power-Down
				Logic

					Terminal Functions
	TERMINAL			I/O	DESCRIPTION
	NAME		NO.
	AGND		5		Analog ground
			3	I	Chip select. Digital input used to enable and disable inputs, active low.
	CS
	DIN		1	I	Serial digital data input
	FS		4	I	Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface.
	OUT		7	O	DAC analog output
	REFIN		6	I	Reference analog input voltage
	SCLK		2	I	Serial digital clock input
	VDD		8		Positive power supply

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS231 ± JUNE 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . 7	V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	± 0.3 V to VDD + 0.3	V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	± 0.3 V to VDD + 0.3	V
Operating free-air temperature range, TA: TLV5623C . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 0°C to 70°C
TLV5623I . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

			MIN	NOM	MAX	UNIT
	Supply voltage, VDD	VDD = 5 V	4.5	5	5.5	V
		VDD = 3 V	2.7	3	3.3	V
	High-level digital input voltage, VIH	VDD = 2.7 V to 5.5 V	2			V
	Low-level digital input voltage, VIL	VDD = 2.7 V to 5.5 V			0.8	V
	Reference voltage, Vref to REFIN terminal	VDD = 5 V (see Note 1)	AGND	2.048	VDD ±1.5	V
	Reference voltage, Vref to REFIN terminal	VDD = 3 V (see Note 1)	AGND	1.024	VDD ± 1.5	V
	Load resistance, RL		2	10		kΩ
	Load capacitance, CL				100	pF
	Clock frequency, fCLK				20	MHz
	Operating free-air temperature, TA	TLV5623C	0		70	°C
		TLV5623I	± 40		85	°C

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ VDD/2 causes clipping of the transfer function.

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)

power supply

		PARAMETER		TEST CONDITIONS		MIN TYP	MAX	UNIT
				VDD = 5 V, VREF = 2.048 V,	Fast	0.9	1.35	mA
				No load,
				All inputs = AGND or VDD,	Slow	0.4	0.6	mA
				DAC latch = 0x800
	IDD	Power supply current
				VDD = 3 V, VREF = 1.024 V	Fast	0.7	1.1	mA
				No load,
				All inputs = AGND or VDD,	Slow	0.3	0.45	mA
				DAC latch = 0x800
		Power down supply current (see Figure 12)				1		μA
	PSRR	Power supply rejection ratio	Zero scale	See Note 2		±68		dB
			Full scale	See Note 3		±68
		Power on threshold voltage, POR				2		V

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) ± EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) ± EG(VDDmin))/VDDmax]

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS231 ± JUNE 1999

electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued)

static DAC specifications RL = 10 kΩ, CL = 100 pF

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
	Resolution		8			bits
INL	Integral nonlinearity	See Note 4		± 0.3	± 0.5	LSB
DNL	Differential nonlinearity	See Note 5		± 0.07	± 0.2	LSB
EZS	Zero-scale error (offset error at zero scale)	See Note 6			± 10	mV
EZS TC	Zero-scale-error temperature coefficient	See Note 7		10		ppm/°C
						% of
EG	Gain error	See Note 8			± 0.6	FS
						voltage
	Gain-error temperature coefficient	See Note 9		10		ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5.The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

6.Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7.Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) ± EZS (Tmin)]/Vref × 106/(Tmax ± Tmin).

8.Gain error is the deviation from the ideal output (2Vref ± 1 LSB) with an output load of 10 kW excluding the effects of the zero-error.

9.Gain temperature coefficient is given by: EG TC = [EG(Tmax) ± EG (Tmin)]/Vref × 106/(Tmax ± Tmin).

output specifications

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VO	Voltage output range	RL = 10 kW	0		VDD±0.1	V
	Output load regulation accuracy	RL = 2 kW, vs 10 kW		±0.1	±0.25	% of FS
						voltage

reference input (REF)

	PARAMETER	TEST CONDITIONS		MIN TYP	MAX	UNIT
VI	Input voltage range			0	VDD±1.5	V
RI	Input resistance			10		MW
CI	Input capacitance			5		pF
	Reference input bandwidth	REFIN = 0.2 Vpp + 1.024 V dc	Slow	525		kHz
			Fast	1.3		MHz
	Reference feed through	REFIN = 1 Vpp at 1 kHz + 1.024 V dc		±75		dB
		(see Note 10)

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

	PARAMETER		TEST CONDITIONS	MIN TYP	MAX	UNIT
IIH	High-level digital input current	VI = VDD			±1	mA
IIL	Low-level digital input current	VI = 0 V			±1	mA
CI	Input capacitance			3		pF

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS231 ± JUNE 1999

operating characteristics over recommended operating free-air temperature range (unless otherwise noted)

analog output dynamic performance

	PARAMETER	TEST CONDITIONS				MIN TYP	MAX	UNIT
ts(FS)	Output settling time, full scale	RL = 10 kW,	CL = 100 pF,		Fast	3	5.5	ms
		See Note 11			Slow	9	20
ts(CC)	Output settling time, code to code	RL = 10 kW,	CL = 100 pF,		Fast	1		ms
		See Note 12			Slow	2		ms
SR	Slew rate	RL = 10 kW,	CL = 100 pF,		Fast	3.6		V/ms
					Slow	0.9
		See Note 13
	Glitch energy	Code transition from 0x7F0 to 0x800				10		nV±s
S/N	Signal to noise					57		dB
		fs = 400 KSPS	fout = 1.1 kHz,
S/(N+D)	Signal to noise + distortion					49		dB
		RL = 10 kW,	CL = 100 pF,
THD	Total harmonic distortion					±50		dB
		BW = 20 kHz
	Spurious free dynamic range					60		dB

NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFF0 or 0xFF0 to 0x020. Not tested, ensured by design.

12.Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, ensured by design.

13.Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

digital input timing requirements

							MIN NOM MAX	UNIT
	tsu(CS±FS)	Setup time,	CS	low before FS↓			10	ns
	tsu(FS±CK)	Setup time, FS low before first negative SCLK edge					8	ns
	tsu(C16±FS)	Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising					10	ns
		edge of FS
		Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before				rising
					CS
	tsu(C16±CS)	edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup					10	ns
		time is between the FS rising edge and CS rising edge.
	twH	Pulse duration, SCLK high					25	ns
	twL	Pulse duration, SCLK low					25	ns
	tsu(D)	Setup time, data ready before SCLK falling edge					8	ns
	th(D)	Hold time, data held valid after SCLK falling edge					5	ns
	twH(FS)	Pulse duration, FS high					20	ns

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TLV5623C, TLV5623I

2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN

SLAS231 ± JUNE 1999

PARAMETER MEASUREMENT INFORMATION

		twL		twH
SCLK	1	2	3	4	5	15	16
	tsu(D)	th(D)
DIN	D15	D14	D13	D12		D1	D0

tsu(FS-CK)

tsu(C16-CS)

tsu(CS-FS)

CS

twH(FS)		tsu(C16-FS)

FS

Figure 1. Timing Diagram

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