Texas Instruments TLV5638QDR, TLV5638QD, TLV5638MJGB, TLV5638MFKB, TLV5638MJG Datasheet

	TLV5638
	2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG
	CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
	SLAS225A ± JUNE 1999 ± REVISED JANUARY 2000
features	D, JG PACKAGE
	(TOP VIEW)

DDual 12-Bit Voltage Output DAC

D	Programmable Internal Reference	DIN					1	8			VDD
D	Programmable Settling Time:	SCLK					2	7			OUTB
	1 s in Fast Mode,		CS				3	6			REF
	3.5 s in Slow Mode	OUTA					4	5			AGND

DCompatible With TMS320 and SPI Serial

Ports

D Differential Nonlinearity <0.5 LSB Typ					FK PACKAGE
					(TOP VIEW)
D	Monotonic Over Temperature			NC	DIN	NC	DD		NC
applications							V
				3	2	1	20		19
	Digital Servo Control Loops
D		NC		4					18		NC
D	Digital Offset and Gain Adjustment	SCLK		5					17		OUTB
D	Industrial Process Control	NC		6					16		NC
D Machine and Motion Control Devices											REF
			CS	7					15
	Mass Storage Devices
D		NC		8					14		NC
description				9	10	11	12		13
				NC	OUTA	NC				NC
							AGND

The TLV5638 is a dual 12-bit voltage output DAC with a flexible 3-wire serial interface. The serial interface allows glueless interface to TMS320 and

SPI , QSPI , and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 12 data bits.

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, the TLV5638 simplifies overall system design.

Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC package to reduce board space in standard commercial, industrial, and automotive temperature ranges. It is also available in JG and FK packages in the military temperature range.

AVAILABLE OPTIONS

			PACKAGE
	TA
		SOIC	CERAMIC DIP	20 PAD LCCC
		(D)	(JG)	(FK)
	0°C to 70°C	TLV5638CD	Ð	Ð
	±40°C to 85°C	TLV5638ID	Ð	Ð
	±40°C to 125°C	TLV5638QD	Ð	Ð
		TLV5638QDR
	±55°C to 125°C	Ð	TLV5638MJG	TLV5638MFK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc.

Microwire is a trademark of National Semiconductor Corporation.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TLV5638

2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS225A ± JUNE 1999 ± REVISED JANUARY 2000

functional block diagram

REF AGND VDD

			PGA With
			Output Enable
		Voltage
		Bandgap
	Power-On	Power
		and Speed
	Reset
		Control
		2
		2
		2-Bit
		Control
DIN		Latch		x2	OUTA
		12	12-Bit	12
			DAC A
SCLK	Serial		Latch
		12
	Interface
	and	Buffer
CS	Control
		12	12-Bit	12
			DAC B
			Latch	x2	OUTB

					Terminal Functions
		TERMINAL		I/O/P	DESCRIPTION
	NAME		NO.
	AGND		5	P	Ground
			3	I	Chip select. Digital input active low, used to enable/disable inputs
	CS
	DIN		1	I	Digital serial data input
	OUT A		4	O	DAC A analog voltage output
	OUT B		7	O	DAC B analog voltage output
	REF		6	I/O	Analog reference voltage input/output
	SCLK		2	I	Digital serial clock input
	VDD		8	P	Positive power supply

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS225A ± JUNE 1999 ± REVISED JANUARY 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . 7	V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to VDD + 0.3	V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to VDD + 0.3	V
Operating free-air temperature range, TA: TLV5638C . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 0°C to 70°C
TLV5638I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . ±40°C to 85°C
TLV5638Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±40°C to 125°C
TLV5638M . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

DISSIPATION RATING TABLE

	PACKAGE	TA ≤ 25°C	DERATING FACTOR	TA = 70°C	TA = 85°C	TA = 125°C
		POWER RATING	ABOVE T = 25°C³	POWER RATING	POWER RATING	POWER RATING
			A
	D	635 mW	5.08 mW/°C	407 mW	330 mW	127 mW
	FK	1375 mW	11.00 mW/°C	880 mW	715 mW	275 mW
	JG	1050 mW	8.40 mW/°C	672 mW	546 mW	210 mW

³This is the inverse of the traditional Junction-to-Ambient thermal Resistance (RΘJA). Thermal Resistances are not production tested and are for informational purposes only.

recommended operating conditions

			MIN	NOM	MAX	UNIT
	Supply voltage, VDD	VDD = 5 V	4.5	5	5.5	V
		VDD = 3 V	2.7	3	3.3	V
	Power on reset, POR		*0.55		*2	V
	High-level digital input voltage, VIH	VDD = 2.7 V to 5.5 V	2			V
	Low-level digital input voltage, VIL	VDD = 2.7 V to 5.5 V			0.8	V
	Reference voltage, Vref to REF terminal	VDD = 5 V (see Note 1)	AGND	2.048	VDD ±1.5	V
	Reference voltage, Vref to REF terminal	VDD = 3 V (see Note 1)	AGND	1.024	VDD ± 1.5	V
	Load resistance, RL		2			kΩ
	Load capacitance, CL				100	pF
	Clock frequency, fCLK				20	MHz
		TLV5638C	0		70
	Operating free-air temperature, TA	TLV5638I	±40		85	°C
		TLV5638Q	±40		125
		TLV5638M	±55		125

*This parameter is not tested for Q and M suffix devices.

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD±0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used.

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3

TLV5638

2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS225A ± JUNE 1999 ± REVISED JANUARY 2000

electrical characteristics over recommended operating conditions, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted)

power supply

						TLV5638C,			TLV5638Q,
	PARAMETER		TEST CONDITIONS				TLV5638I		TLV5638M		UNIT
						MIN	TYP	MAX	MIN TYP MAX
				VDD = 5 V,	Fast		4.3	5.2	4.3	5.4	mA
				Int. ref.	Slow		2.2	2.7	2.2	2.7
		No load,		VDD = 3 V,	Fast		3.8	4.7	3.8	4.9	mA
IDD	Power supply current	All inputs = AGND		Int. ref.	Slow		1.8	2.3	1.8	2.3
		or VDD,		VDD = 5 V,	Fast		3.9	4.8	3.9	5.0	mA
		DAC latch = 0x800
				Ext. ref.	Slow		1.8	2.2	1.8	2.2
				VDD = 3 V,	Fast		3.5	4.3	3.5	4.5	mA
				Ext. ref.	Slow		1.5	1.9	1.5	1.9
	Power-down supply current						0.01	10	0.01	10	µA
PSRR	Power supply rejection ratio	Zero scale, See Note 2					±65		±65		dB
		Full scale,	See Note 3				±65		±65

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by:

PSRR = 20 log [(EZS(VDDmax) ± EZS(VDDmin))/VDDmax]

3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) ± EG(VDDmin))/VDDmax]

static DAC specifications

		PARAMETER	TEST CONDITIONS		MIN TYP	MAX	UNIT
		Resolution			12		bits
	INL	Integral nonlinearity, end point adjusted	See Note 4	C and I suffixes	±1.7	±4	LSB
				Q and M suffixes	±1.7	±6	LSB
	DNL	Differential nonlinearity	See Note 5		±0.4	±1	LSB
	EZS	Zero-scale error (offset error at zero scale)	See Note 6			±24	mV
	EZS TC	Zero-scale-error temperature coefficient	See Note 7		10		ppm/°C
	EG	Gain error	See Note 8			±0.6	% full
							scale V
	EG TC	Gain error temperature coefficient	See Note 9		10		ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 32 to 4095.

5.The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

6.Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7.Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) ± EZS (Tmin)]/Vref × 106/(Tmax ± Tmin).

8.Gain error is the deviation from the ideal output (2Vref ± 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.

9.Gain temperature coefficient is given by: EG TC = [EG(Tmax) ± EG (Tmin)]/Vref × 106/(Tmax ± Tmin).

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLV5638 2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS225A ± JUNE 1999 ± REVISED JANUARY 2000

electrical characteristics over recommended operating conditions, Vref = 2.048 V, Vref = 1.024 V (unless otherwise noted) (continued)

output specifications

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VO	Output voltage	RL = 10 kΩ	0		VDD±0.4	V
	Output load regulation accuracy	VO = 4.096 V, 2.048 V, RL = 2 kΩ			± 0.25	% full
						scale V

reference pin configured as output (REF)

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
Vref(OUTL)	Low reference voltage		1.003	1.024	1.045	V
Vref(OUTH)	High reference voltage	VDD > 4.75 V	2.027	2.048	2.069	V
Iref(source)	Output source current				1	mA
Iref(sink)	Output sink current		±1			mA
	Load capacitance				100	pF
PSRR	Power supply rejection ratio			±65		dB

reference pin configured as input (REF)

	PARAMETER	TEST CONDITIONS		MIN TYP	MAX	UNIT
VI	Input voltage			0	VDD±1.5	V
RI	Input resistance			10		MΩ
CI	Input capacitance			5		pF
	Reference input bandwidth	REF = 0.2 Vpp + 1.024 V dc	Fast	1.3		MHz
			Slow	525		kHz
	Reference feedthrough	REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10)		± 80		dB

NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.

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5

TLV5638

2.7 V TO 5.5 V LOW POWER DUAL 12-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN

SLAS225A ± JUNE 1999 ± REVISED JANUARY 2000

electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued)

digital inputs

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
IIH	High-level digital input current	VI = VDD			1	µA
IIL	Low-level digital input current	VI = 0 V	±1			µA
Ci	Input capacitance			8		pF

analog output dynamic performance

	PARAMETER	TEST CONDITIONS			MIN	TYP	MAX	UNIT
ts(FS)	Output settling time, full scale	RL = 10 kΩ,	CL = 100 pF,	Fast		1	3	µs
		See Note 11		Slow		3.5	7
ts(CC)	Output settling time, code to code	RL = 10 kΩ,	CL = 100 pF,	Fast		0.5	1.5	µs
		See Note 12		Slow		1	2
SR	Slew rate	RL = 10 kΩ,	CL = 100 pF,	Fast		12		V/µs
				Slow		1.8
		See Note 13
	Glitch energy	DIN = 0 to 1, FCLK = 100 kHz,				5		nV±s
		CS = VDD
SNR	Signal-to-noise ratio				69	74
S/(N+D)	Signal-to-noise + distortion	fs = 480 kSPS,	fout = 1 kHz,		58	67		dB
THD	Total harmonic distortion	RL = 10 kΩ,	CL = 100 pF			±69	±57
	Spurious free dynamic range				57	72

NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDF and 0xFDF to 0x020 respectively. Not tested, assured by design.

12.Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design.

13.Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

digital input timing requirements

						MIN NOM MAX	UNIT
tsu(CS±CK)	Setup time,		low before first negative SCLK edge			10	ns
		CS
t	Setup time, 16th negative SCLK edge (when D0 is sampled) before				rising edge	10	ns
				CS
su(C16-CS)
twH	SCLK pulse width high					25	ns
twL	SCLK pulse width low					25	ns
tsu(D)	Setup time, data ready before SCLK falling edge					10	ns
th(D)	Hold time, data held valid after SCLK falling edge					5	ns

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