Texas Instruments TMX320VC5409PGE100, TMX320VC5409GGU100, TMS320VC5409GGU100, TMS320VC5409GGU-80, TMS320VC5409PGE100 Datasheet

TMS320VC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

Advanced Multibus Architecture With Three Separate 16-Bit Data Memory Buses and One Program Memory Bus

40-Bit Arithmetic Logic Unit (ALU), Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators

17- ×17-Bit Parallel Multiplier Coupled to a

40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation

Compare, Select, and Store Unit (CSSU) for the Add/Compare Selection of the Viterbi Operator

Exponent Encoder to Compute an Exponent Value of a 40-Bit Accumulator Value in a Single Cycle

Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)

Data Bus With a Bus-Holder Feature

Extended Addressing Mode for 8M × 16-Bit

Maximum Addressable External Program Space

16K x 16-Bit On-Chip ROM

32K x 16-Bit Dual-Access On-Chip RAM

Single-Instruction-Repeat and Block-Repeat Operations for Program Code

Block-Memory-Move Instructions for Better Program and Data Management

Instructions With a 32-Bit Long Word Operand

Instructions With Twoor Three-Operand Reads

Arithmetic Instructions With Parallel Store and Parallel Load

Conditional Store Instructions

Fast Return From Interrupt

On-Chip Peripherals

±Software-Programmable Wait-State Generator and Programmable Bank Switching

±On-Chip Phase-Locked Loop (PLL) Clock Generator With Internal Oscillator or External Clock Source

±Three Multichannel Buffered Serial Ports (McBSPs)

±Enhanced 8-Bit Parallel Host-Port Interface With 16-Bit Data/Addressing

±One 16-Bit Timer

±Six-Channel Direct Memory Access (DMA) Controller

Power Consumption Control With IDLE1, IDLE2, and IDLE3 Instructions With Power-Down Modes

CLKOUT Off Control to Disable CLKOUT

On-Chip Scan-Based Emulation Logic, IEEE Std 1149.1² (JTAG) Boundary Scan Logic

12.5-ns Single-Cycle Fixed-Point Instruction Execution Time (80 MIPS) for 3.3-V Power Supply (1.8-V Core)

10-ns Single-Cycle Fixed-Point Instruction Execution Time (100 MIPS) for 3.3-V Power Supply (1.8-V Core)

Available in a 144-Pin Plastic Thin Quad Flatpack (TQFP) (PGE Suffix) and a 144-Pin Ball Grid Array (BGA) (GGU Suffix)

NOTE:This data sheet is designed to be used in conjunction with the TMS320C5000 DSP Family Functional Overview (literature number SPRU307).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

² IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

PRODUCTION DATA information is current as of publication date.	Copyright 2000, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443	1

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

		Table of Contents
	Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 2	Internal Oscillator with External Crystal . . . . . . . .									40
	Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 5	Divide-by-Two/Divide-by-Four Clock Option . . . .									41
	Terminal Functions	6	Multiply-by-N Clock Option . . . . . . . . . . . . . . . . . . .									42
			Memory and Parallel I/O Interface Timing									43
	Memory	11
			Timing	For Externally Generated Wait States								49
	On-chip Peripherals	15
			HOLD		and HOLDA Timings							53
	Memory-mapped Registers . . . . . . . . . . . . . . .	30. . . . .
			Reset, BIO, Interrupt, and MP/MC Timings									55
	McBSP Control Registers And Subaddresses	. . . . 33
			Instruction Acquisition (IAQ), Interrupt
	DMA Subbank Addressed Registers	33
			Acknowledge (IACK), External Flag (XF),
	Interrupts	35
			and TOUT Timings . . . . . . . . . . . . . . . . . . . . .									57
	Documentation Support . . . . . . . . . . . . . . . . . .	. . . . . 37	Multichannel Buffered Serial Port Timing . . . . . . .									59
	Absolute Maximum Ratings . . . . . . . . . . . . . .	. . . . . 38	HPI8 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .									67
	Recommended Operating Conditions . . . . . .	. . . . . 38	HPI16 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .									72
	Electrical Characteristics	39	Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . .									76
	Parameter Measurement Information . . . . . . .	. . . . . 39

description

The TMS320VC5409 fixed-point, digital signal processor (DSP) (hereafter referred to as the '5409 unless otherwise specified) is based on an advanced modified Harvard architecture that has one program memory bus and three data memory buses. This processor provides an arithmetic logic unit (ALU) with a high degree of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The basis of the operational flexibility and speed of this DSP is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing the high degree of parallelism. Two read operations and one write operation can be performed in a single cycle. Instructions with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle. In addition, the '5409 includes the control mechanisms to manage interrupts, repeated operations, and function calls.

2	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

TMS320VC5409 PGE PACKAGE²³

(TOP VIEW)

															SS				A21				DD				A9					A8				A7				A6				A5					A4				HD6				A3				A2					A1				A0			DD				HDS2					SS				HDS1				SS				DD				HD5				D15				D14				D13			HD4				D12			D11			D10			D9			D8			D7				D6				DD				SS				A20				A19
															V								CV																																																		DV							V									V					CV																																														DV				V
			VSS								144							143				142				141				140					139				138				137				136					135				134				133				132				131					130			129				128					127			126					125				124				123				122				121				120			119				118			117			116			115			114			113				112				111				110		109							A18
											1																																																																																																																																										108
			A22								2																																																																																																																																										107							A17
			VSS								3																																																																																																																																										106							VSS
	DVDD
											4																																																																																																																																										105							A16
			A10								5																																																																																																																																										104							D5
			HD7								6																																																																																																																																										103							D4
				A11							7																																																																																																																																										102							D3
			A12								8																																																																																																																																										101							D2
			A13
											9																																																																																																																																										100							D1
			A14
											10																																																																																																																																										99							D0
			A15								11																																																																																																																																										98							RS
	CVDD
											12																																																																																																																																										97							X2/CLKIN
			HAS								13																																																																																																																																										96							X1
			VSS								14																																																																																																																																										95							HD3
			VSS								15																																																																																																																																										94							CLKOUT
	CVDD										16																																																																																																																																										93							V
																																																																																																																																																												SS
			HCS
											17																																																																																																																																										92							HPIENA
		HR/W									18																																																																																																																																										91							CVDD
	READY
											19																																																																																																																																										90							VSS
						PS
											20																																																																																																																																										89							TMS
						DS					21																																																																																																																																										88							TCK
							IS				22																																																																																																																																										87							TRST
			R/W								23																																																																																																																																										86							TDI
	MSTRB										24																																																																																																																																										85							TDO
	IOSTRB
											25																																																																																																																																										84							EMU1/OFF
			MSC								26																																																																																																																																										83							EMU0
						XF					27																																																																																																																																										82							TOUT
	HOLDA										28																																																																																																																																										81							HD2
				IAQ							29																																																																																																																																										80							HPI16
		HOLD									30																																																																																																																																										79							CLKMD3
																																																																																																																																																												CLKMD2
				BIO							31																																																																																																																																										78
																																																																																																																																																												CLKMD1
	MP/MC										32																																																																																																																																										77
	DVDD										33																																																																																																																																										76							VSS
			VSS								34																																																																																																																																										75							DVDD
		BDR1									35																																																																																																																																										74							BDX1
	BFSR1										36																																																																																																																																										73							BFSX1
											37							38				39				40				41					42				43				44				45					46				47				48				49				50					51			52				53					54			55					56				57				58				59				60				61			62				63			64			65			66			67			68				69				70				71		72
												V							BCLKR1				HCNTL0				V					BCLKR0				BCLKR2				BFSR0				BFSR2					BDR0				HCNTL1				BDR2				BCLKX0					BCLKX2			V				HINT				CV					BFSX0			BFSX2					HRDY				DV				V				HD0				BDX0				BDX2			IACK				HBIL NMI						INT0			INT1			INT2			INT3				CV				HD1				V				BCLKX1		V
															SS												SS																																											SS							DD																	DD				SS																																						DD								SS								SS

NOTE: DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

The TMS320VC5409PGE (144-pin TQFP) package is footprint-compatible with the 'LC548, 'LC/VC549, and 'VC5410 devices.

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

3

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

TMS320VC5409 GGU PACKAGE

(BOTTOM VIEW)

13

12

11 10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

The pin assignments table to follow lists each signal quadrant and BGA ball number for the TMS320VC5409GGU (144-pin BGA package) which is footprint-compatible with the 'LC548, 'LC/VC549, and 'VC5410 devices.

4	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

Pin Assignments for the TMS320VC5409GGU (144-Pin BGA Package)²

SIGNAL

BGA BALL #

SIGNAL

BGA BALL #

SIGNAL

BGA BALL #

SIGNAL

BGA BALL #

QUADRANT 1

QUADRANT 2

QUADRANT 3

QUADRANT 4

VSS

A1

BFSX1

N13

VSS

N1

A19

A13

A22

B1

BDX1

M13

BCLKR1

N2

A20

A12

VSS

C2

DVDD

L12

HCNTL0

M3

VSS

B11

DVDD

C1

VSS

L13

VSS

N3

DVDD

A11

A10

D4

CLKMD1

K10

BCLKR0

K4

D6

D10

HD7

D3

CLKMD2

K11

BCLKR2

L4

D7

C10

A11

D2

CLKMD3

K12

BFSR0

M4

D8

B10

A12

D1

HPI16

K13

BFSR2

N4

D9

A10

A13

E4

HD2

J10

BDR0

K5

D10

D9

A14

E3

TOUT

J11

HCNTL1

L5

D11

C9

A15

E2

EMU0

J12

BDR2

M5

D12

B9

CVDD

E1

EMU1/OFF

J13

BCLKX0

N5

HD4

A9

F4

TDO

H10

BCLKX2

K6

D13

D8

HAS

VSS

F3

TDI

H11

VSS

L6

D14

C8

VSS

F2

H12

M6

D15

B8

TRST

HINT

CVDD

F1

TCK

H13

CVDD

N6

HD5

A8

G2

TMS

G12

BFSX0

M7

CVDD

B7

HCS

G1

VSS

G13

BFSX2

N7

VSS

A7

HR/W

READY

G3

CVDD

G11

HRDY

L7

C7

HDS1

G4

HPIENA

G10

DVDD

K7

VSS

D7

PS

H1

VSS

F13

VSS

N8

A6

DS

HDS2

H2

CLKOUT

F12

HD0

M8

DVDD

B6

IS

H3

HD3

F11

BDX0

L8

A0

C6

R/W

H4

X1

F10

BDX2

K8

A1

D6

MSTRB

J1

X2/CLKIN

E13

N9

A2

A5

IOSTRB

IACK

J2

E12

HBIL

M9

A3

B5

MSC

RS

XF

J3

D0

E11

L9

HD6

C5

NMI

J4

D1

E10

K9

A4

D5

HOLDA

INT0

K1

D2

D13

N10

A5

A4

IAQ

INT1

K2

D3

D12

M10

A6

B4

HOLD

INT2

K3

D4

D11

L10

A7

C4

BIO

INT3

L1

D5

C13

CVDD

N11

A8

A3

MP/MC

DVDD

L2

A16

C12

HD1

M11

A9

B3

VSS

L3

VSS

C11

VSS

L11

CVDD

C3

BDR1

M1

A17

B13

BCLKX1

N12

A21

A2

BFSR1

M2

A18

B12

VSS

M12

VSS

B2

²DVDD is the power supply for the I/O pins while CVDD is the power supply for the core CPU. VSS is the ground for both the I/O pins and the core CPU.

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

5

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

terminal functions

The '5409 signal descriptions table lists each pin name, function, and operating mode(s) for the '5409 device. Some of the '5409 pins can be configured for one of two functions; a primary function and a secondary function. The names of these pins in secondary mode are shaded in grey in the following table.

Terminal Functions

TERMINAL

INTERNAL

I/O²

DESCRIPTION

NAME

PIN STATE

DATA SIGNALS

A22

(MSB)

O/Z

A21

A20

A19

A18

A17

A16

A15

A14

A13

Parallel address bus A22 [most significant bit (MSB)] through A0 [least significant bit (LSB)]. The

A12

Bus holders

lower sixteen address pins (A15 to A0) are multiplexed to address all external memory (program,

A11

available

data) or I/O while the upper seven address pins (A22 to A16) are only used to address external

A10

(A15±A0)

program space. These pins are placed in the high-impedance state when the hold mode is enabled,

A9

or when OFF is low.

A8

A7

A6

A5

A4

A3

A2

A1

A0

(LSB)

D15

(MSB)

I/O/Z

D14

D13

D12

Parallel data bus D15 (MSB) through D0 (LSB). The sixteen data pins (D15 to D0) are multiplexed

D11

to transfer data between the core CPU and external data/program memory or I/O devices. The data

D10

bus is placed in the high-impedance state when not outputting or when RS or HOLD is asserted.

D9

The data bus also goes into the high-impedance state when OFF is low.

D8

Bus holders

D7

available

The data bus has bus holders to reduce the static power dissipation caused by floating, unused

D6

pins. These bus holders also eliminate the need for external bias resistors on unused pins. When

D5

the data bus is not being driven by the '5409, the bus holders keep the pins at the previous logic

D4

level. The data bus holders on the '5409 are disabled at reset and can be enabled/disabled via the

D3

BH bit of the bank-switching control register (BSCR).

D2

D1

D0

(LSB)

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

Interrupt acknowledge signal.

IACK

indicates receipt of an interrupt and that the program counter

IACK

O/Z

is fetching the interrupt vector location designated by A15±A0. IACK also goes into the

high-impedance state when OFF is low.

INT0

INT1

Schmitt

I

External user interrupts.

INT0±INT3 are prioritized and are maskable by the interrupt mask register

INT2

trigger

and the interrupt mode bit. INT0 ±INT3 can be polled and reset by way of the interrupt flag register.

INT3

² I = Input, O = Output, Z = High-impedance, S = Supply

6	POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

Terminal Functions (Continued)

TERMINAL

INTERNAL

I/O²

DESCRIPTION

NAME

PIN STATE

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS (CONTINUED)

Schmitt

I

Nonmaskable interrupt.

NMI

is an external interrupt that cannot be masked by way of the INTM or

NMI

trigger

the IMR. When NMI is activated, the processor traps to the appropriate vector location.

Schmitt

Reset.

RS

causes the DSP to terminate execution and causes a reinitialization of the CPU and

RS

I

peripherals. When RS is brought to a high level, execution begins at location 0FF80h of program

trigger

memory. RS affects various registers and status bits.

Microprocessor/microcomputer mode select. If active low at reset, microcomputer mode is

selected, and the internal program ROM is mapped into the upper program memory space. If the

MP/MC

I

pin is driven high during reset, microprocessor mode is selected, and the on-chip ROM is removed

from program space. MP/MC is only sampled at reset, and the MP/MC bit of the PMST register can

override the mode that is selected at reset.

MULTIPROCESSING SIGNALS

Branch control. A branch can be conditionally executed when

BIO

is active. If low, the processor

Schmitt

executes the conditional instruction. For the XC instruction, the BIO condition is sampled during

BIO

I

trigger

the decode phase of the pipeline; all other instructions sample BIO during the read phase of the

pipeline.

External flag output (latched software-programmable signal). XF is set high by the SSBX XF

XF

O/Z

instruction, set low by the RSBX XF instruction or by loading ST1. XF is used for signaling other

processors in multiprocessor configurations or used as a general-purpose output pin. XF goes into

the high-impedance state when OFF is low, and is set high at reset.

MEMORY CONTROL SIGNALS

Data, program, and I/O space select signals.

DS,

PS,

and

IS

are always high unless driven low for

DS

accessing a particular external memory space. Active period corresponds to valid address

PS

O/Z

information. DS, PS, and IS are placed into the high-impedance state in the hold mode; the signals

IS

also go into the high-impedance state when OFF is low.

Memory strobe signal.

MSTRB

is always high unless low-level asserted to indicate an external bus

MSTRB

O/Z

access to data or program memory. MSTRB is placed in the high-impedance state in the hold mode;

it also goes into the high-impedance state when OFF is low.

Data ready. READY indicates that an external device is prepared for a bus transaction to be

READY

I

completed. If the device is not ready (READY is low), the processor waits one cycle and checks

READY again. Note that the processor performs ready detection if at least two software wait states

are programmed. The READY signal is not sampled until the completion of the software wait states.

Read/write signal. R/W

indicates transfer direction during communication to an external device.

R/W is normally in the read mode (high), unless it is asserted low when the DSP performs a write

R/W

O/Z

operation. R/W is placed in the high-impedance state in hold mode; it also goes into the

high-impedance state when OFF is low.

I/O strobe signal.

IOSTRB

is always high unless low-level asserted to indicate an external bus

IOSTRB

O/Z

access to an I/O device. IOSTRB is placed in the high-impedance state in the hold mode; it also

goes into the high-impedance state when OFF is low.

Hold.

HOLD

is asserted to request control of the address, data, and control lines. When

HOLD

I

acknowledged by the 'C54x, these lines go into the high-impedance state.

Hold acknowledge.

HOLDA

indicates that the '5409 is in a hold state and that the address, data,

HOLDA

O/Z

and control lines are in the high-impedance state, allowing the external memory interface to be

accessed by other devices. HOLDA also goes into the high-impedance state when OFF is low.

Microstate complete.

MSC

indicates completion of all software wait states. When two or more

software wait states are enabled, the MSC pin goes low during the last of these wait states. If

MSC

O/Z

connected to the READY input, MSC forces one external wait state after the last internal wait state

is completed. MSC also goes into the high-impedance state when OFF is low.

Instruction acquisition signal.

IAQ

is asserted (active low) when there is an instruction address on

IAQ

O/Z

the address bus. IAQ goes into the high-impedance state when OFF is low.

² I = Input, O = Output, Z = High-impedance, S = Supply

POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251±1443

7

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

				Terminal Functions (Continued)
TERMINAL	INTERNAL	I/O²				DESCRIPTION
NAME	PIN STATE
				OSCILLATOR/TIMER SIGNALS
				Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal
CLKOUT		O/Z		machine cycle is bounded by rising edges of this signal. CLKOUT also goes into the
				high-impedance state when	OFF	is low.
CLKMD1				Clock mode select signals. These inputs select the mode that the clock generator is initialized to
	Schmitt			after reset. The logic levels of CLKMD1±CLKMD3 are latched when the reset pin is low, and the
CLKMD2		I
	trigger			clock mode register is initialized to the selected mode. After reset, the clock mode can be changed
CLKMD3
				through software, but the clock mode select signals have no effect until the device is reset again.
X2/CLKIN	Schmitt	I		Clock/oscillator input. If the internal oscillator is not being used, X2/CLKIN functions as the clock
	trigger			input.
X1		O		Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should
				be left unconnected. X1 does not go into the high-impedance state when OFF is low.
TOUT		O/Z		Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is
				one CLKOUT cycle wide. TOUT also goes into the high-impedance state when OFF is low.
			MULTICHANNEL BUFFERED SERIAL PORT SIGNALS
				Receive clocks. BCLKR serves as the serial shift clock for the buffered serial-port receiver. Input
BCLKR0				from an external clock source for clocking data into the McBSP. When not being used as a clock,
BCLKR1	Schmitt	I/O/Z		these pins can be used as general-purpose I/O by setting RIOEN = 1.
BCLKR2	trigger
				BCLKR can be configured as an output by the way of the CLKRM bit in the PCR register.
BDR0				Buffered serial data receive (input) pin. When not being used as data-receive pins, these pins can
BDR1		I
				be used as general-purpose I/O by setting RIOEN = 1.
BDR2
BFSR0				Frame synchronization pin for buffered serial-port input data. The BFSR pulse initiates the
BFSR1		I/O/Z		receive-data process over the BDR pin. When not being used as data-receive synchronization pins,
BFSR2				these pins can be used as general-purpose I/O by setting RIOEN = 1.
				Transmit clocks. Clock signal used to clock data from the transmit register. This pin can also be
BCLKX0				configured as an input by setting the CLKXM = 0 in the PCR register. When not being used as a
BCLKX1	Schmitt	I/O/Z		clock, these pins can be used as general-purpose I/O by setting XIOEN = 1.
BCLKX2	trigger
				These pins are placed into the high-impedance state when			OFF	is low.
BDX0				Buffered serial-port transmit (output) pin. When not being used as data-transmit pins, these pins
				can be used as general-purpose I/O by setting XIOEN = 1.
BDX1		O/Z
BDX2
				These pins are placed into the high-impedance state when OFF is low.
				Buffered serial-port frame synchronization pin for transmitting data. The BFSX pulse initiates the
BFSX0				transmit-data process over BDX pin. If RS is asserted when BFSX is configured as output, then
				BFSX is turned into input mode by the reset operation. When not being used as data-transmit
BFSX1		I/O/Z
				synchronization pins, these pins can be used as general-purpose I/O by setting XIOEN = 1.
BFSX2
				These pins are placed into the high-impedance state when			OFF	is low.
² I = Input, O = Output, Z = High-impedance, S = Supply

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TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

Terminal Functions (Continued)

TERMINAL

INTERNAL

I/O²

DESCRIPTION

NAME

PIN STATE

HOST-PORT INTERFACE SIGNALS

SECONDARY

PRIMARY

These pins can be used to address internal memory via the HPI

when the HPI16 pin is high. The sixteen address pins, A15 to A0,

are multiplexed to transfer address between the core CPU and

external data/program memory, I/O devices, or HPI in 16-bit mode.

HA15 ± HA0

Bus holders

I/O/Z

A15 ± A0

O/Z

The address bus includes bus holders to reduce the static power

available

dissipation caused by floating, unused pins. The bus holders also

eliminate the need for external bias resistors on unused pins. When

the address bus is not being driven by the '5409, the bus holders

keep the pins at the logic level that was most recently driven. The

address bus holders of the '5409 are disabled at reset, and can be

enabled/disabled via the HBH bit of the BSCR.

These pins can be used to read/write internal memory via the HPI

when the HPI16 pin is high. The sixteen data pins, D15 to D0, are

multiplexed to transfer data between the core CPU and external

data/program memory, I/O devices, or HPI in 16-bit mode. The data

bus is placed in the high-impedance state when not outputting or

when RS or

HOLD

is asserted. The data bus also goes into the

Bus holders

high-impedance state when OFF is low.

HD15 ± HD0

available

I/O/Z

D15 ± D0

O/Z

The data bus includes bus holders to reduce the static power

dissipation caused by floating, unused pins. The bus holders also

eliminate the need for external bias resistors on unused pins. When

the data bus is not being driven by the '5409, the bus holders keep

the pins at the logic level that was most recently driven. The data

bus holders of the '5409 are disabled at reset, and can be

enabled/disabled via the BH bit of the BSCR.

Parallel bidirectional data bus. When the HPI is disabled or when the HPI16 pin is high, these pins

can also be used as general-purpose I/O pins. HD7±HD0 are placed in the high-impedance state

when not outputting data or when OFF is low.

HD7 ± HD0

Bus holders

I/O/Z

The HPI data bus includes bus holders to reduce the static power dissipation caused by floating,

available

unused pins. When the HPI data bus is not being driven by the '5409, the bus holders keep the pins

at the logic level that was most recently driven. The HPI data bus holders are disabled at reset. In

8-bit mode the bus holders can be enabled/disabled via the HBH bit of the BSCR. In 16-bit mode

the bus holders are always active on the HD7±HD0 pins.

HCNTL0

Pullup

I

Control. HCNTL0 and HCNTL1 select a host access to one of the three HPI registers. The control

HCNTL1

resistor

inputs have internal pullup resistors that are only enabled when HPIENA = 0.

HBIL

Pullup

I

Byte identification. HBIL identifies the first or second byte of transfer. The HBIL input has an internal

resistor

pullup resistor that is only enabled when HPIENA = 0.

Schmitt

Chip select. HCS is the select input for the HPI and must be driven low during accesses. The

HCS

trigger/pullup

I

chip-select input has an internal pullup resistor that is only enabled when HPIENA = 0.

resistor

Schmitt

HDS1

Data strobe. HDS1 and HDS2 are driven by the host read and write strobes to control transfers.

trigger/pullup

I

HDS2

The strobe inputs have internal pullup resistors that are only enabled when HPIENA = 0.

resistor

Schmitt

Address strobe. Hosts with multiplexed address and data pins require HAS to latch the address in

HAS

trigger/pullup

I

the HPIA register. HAS has an internal pullup resistor that is only enabled when HPIENA = 0.

resistor

² I = Input, O = Output, Z = High-impedance, S = Supply

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9

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

Terminal Functions (Continued)

TERMINAL

INTERNAL

I/O²

DESCRIPTION

NAME

PIN STATE

HOST-PORT INTERFACE SIGNALS (CONTINUED)

Pullup

Read/write. HR/W

controls the direction of an HPI transfer. R/W has an internal pullup resistor that

HR/W

I

resistor

is only enabled when HPIENA = 0.

HRDY

O/Z

Ready. The ready output informs the host when the HPI is ready for the next transfer. HRDY goes

into the high-impedance state when OFF is low.

Interrupt. This output is used to interrupt the host. When the DSP is in reset,

is driven high.

HINT

HINT

O/Z

The signal goes into the high-impedance state when OFF is low.

HPI module select. HPIENA must be driven high during reset to enable the HPI. An internal

HPIENA

Pulldown

I

pulldown resistor is always active and the HPIENA pin is sampled on the rising edge of RS. If

resistor

HPIENA is left open or is driven low during reset, the HPI module is disabled. Once the HPI is

disabled, the HPIENA pin has no effect until the '5409 is reset.

HPI 16-bit select pin (internal pulldown, default HPI8). HPI16 = 1 selects the non-multiplexed mode.

The non-multiplexed mode allows hosts with separate address/data buses to access the HPI

address range via the 16 address pins (A15±A0). 16-bit data is also accessible through pins D0

HPI16

Pulldown

I

through D15. Host-to-DSP and DSP-to-Host interrupts are not supported. There are no HPIC and

resistor

HPIA register accesses in the non-multiplexed mode.

The HPI16 pin is sampled at RESET. The user should never change the value of the HPI16 pin while

the RESET signal is HIGH.

SUPPLY PINS

CVDD

S

+VDD. Dedicated 1.8-V power supply for the core CPU

DVDD

S

+VDD. Dedicated 3.3-V power supply for the I/O pins

VSS

S

Ground

TEST PINS

Schmitt

IEEE standard 1149.1 test clock. TCK is normally a free-running clock signal with a 50% duty cycle.

The changes on the test access port (TAP) of input signals TMS and TDI are clocked into the TAP

TCK

trigger/pullup

I

controller, instruction register, or selected test data register on the rising edge of TCK. Changes at

resistor

the TAP output signal (TDO) occur on the falling edge of TCK.

TDI

Pullup

I

IEEE standard 1149.1 test data input pin with internal pullup device. TDI is clocked into the selected

resistor

register (instruction or data) on a rising edge of TCK.

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data)

TDO

O/Z

are shifted out of TDO on the falling edge of TCK. TDO is in the high-impedance state except when

the scanning of data is in progress. TDO also goes into the high-impedance state when OFF is low.

TMS

Pullup

I

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is

resistor

clocked into the TAP controller on the rising edge of TCK.

IEEE standard 1149.1 test reset.

TRST, when high, gives the IEEE standard 1149.1 scan system

Pulldown

control of the operations of the device. If TRST is not connected or is driven low, the device operates

TRST

I

resistor

in its functional mode, and the IEEE standard 1149.1 signals are ignored. Pin with internal pulldown

device.

² I = Input, O = Output, Z = High-impedance, S = Supply

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TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

Terminal Functions (Continued)

TERMINAL

INTERNAL

I/O²

DESCRIPTION

NAME

PIN STATE

TEST PINS (CONTINUED)

Emulator 0 pin. When

TRST

is driven low, EMU0 must be high for activation of the

OFF

condition.

EMU0

I/O/Z

When TRST is driven high, EMU0 is used as an interrupt to or from the emulator system and is

defined as input/output by way of the IEEE standard 1149.1 scan system.

Emulator 1 pin/disable all outputs. When

TRST

is driven high, EMU1/OFF

is used as an interrupt

to or from the emulator system and is defined as input/output by way of the IEEE standard 1149.1

scan system. When TRST is driven low, EMU1/OFF is configured as

OFF.

The EMU1/OFF signal,

when active low, puts all output drivers into the high-impedance state. Note that OFF is used

EMU1/OFF

I/O/Z

exclusively for testing and emulation purposes (not for multiprocessing applications). Therefore,

for the OFF feature, the following apply:

TRST = low

EMU0 = high

EMU1/OFF = low

² I = Input, O = Output, Z = High-impedance, S = Supply

memory

The '5409 device provides both on-chip ROM and RAM memories to aid in system performance and integration.

on-chip ROM with bootloader

A bootloader is available in the standard '5409 on-chip ROM. This bootloader can be used to automatically transfer user code from an external source to anywhere in the program memory at power up. If the MP/MC pin is sampled low during a hardware reset, execution begins at location FF80h of the on-chip ROM. This location contains a branch instruction to the start of the bootloader program. The standard '5409 bootloader provides different ways to download the code to accommodate various system requirements:

Parallel from 8-bit or 16-bit-wide EPROM

Parallel from I/O space 8-bit or 16-bit mode

Serial boot from serial ports 8-bit or 16-bit mode

Host-port interface boot

SPI serial EEPROM 8-bit boot mode

The standard on-chip ROM layout is shown in Table 1.

on-chip memory security

The '5409 features a 16K-word × 16-bit on-chip maskable ROM. Customers can arrange to have the ROM of the '5409 programmed with contents unique to any particular application. A security option is available to protect a custom ROM. The ROM and ROM/RAM security options are available on the '5409. These security options are described in the TMS320C54x DSP CPU and Peripherals Reference Set, Volume 1 (literature number SPRU131). When the security options are enabled, JTAG emulation is inhibited or nonfunctional.

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11

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

on-chip ROM with bootloader (continued)

	Table 1. Standard On-Chip ROM Layout²
ADDRESS RANGE		DESCRIPTION
0x0000h ± 0xBFFFh		External program space
0xC000h ± 0xF7FFh		Reserved
0xF800h ± 0xFBFFh		Bootloader
0xFC00h ± 0xFEFFh		Reserved
		Reserved²
0xFF00h ± 0xFF7Fh
0xFF80h ± 0xFFFFh		Interrupt vector table

²In the 'VC5409 ROM, 128 words are reserved for factory device-testing purposes. Application code to be implemented in on-chip ROM must reserve these 128 words at addresses FF00h±FF7Fh in program space.

on-chip RAM

The '5409 device contains 32K ×16-bit of on-chip dual-access RAM (DARAM). The DARAM is composed of four blocks of 8K words each. Each block in the DARAM can support two reads in one cycle, or a read and a write in one cycle. The DARAM is located in the address range 0080h±7FFFh in data space, and can be mapped into program/data space by setting the OVLY bit to one.

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TMS320VC5409 FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

memory map

Hex Page 0 Program 0000

Reserved (OVLY = 1)

External (OVLY = 0)

007F

0080

On-Chip DARAM² (OVLY = 1)

External (OVLY = 0)

7FFF

8000

External

FF7F

FF80

Interrupts

(External)

FFFF

MP/MC= 1

(Microprocessor Mode)

Hex Page 0 Program 0000

Reserved (OVLY = 1)

External (OVLY = 0)

007F

0080

On-Chip DARAM² (OVLY = 1)

External (OVLY = 0)

7FFF

8000

External

BFFF

C000

On-Chip ROM

(16K Words)

FEFF

FF00

Reserved

FF7F

FF80

Interrupts (On-Chip)

FFFF

MP/MC= 0

(Microcomputer Mode)

Hex	Data
0000	Memory-
	Mapped
005F	Registers
0060	Scratch-Pad
	RAM
007F
0080
	On-Chip
	DARAM²
	(32K words)
7FFF
8000	External
BFFF
C000	ROM
	(DROM=1)
	or External
	(DROM=0)
FEFF
FF00	Reserved
	(DROM=1)
	or External
FFFF	(DROM=0)

²DARAM0= 0060h ± 1FFFh, DARAM1= 2000h ± 3FFFh DARAM2= 4000h ± 5FFFh, DARAM3= 6000h ± 7FFFh

Figure 1. Memory Map

relocatable interrupt vector table

The reset, interrupt, and trap vectors are addressed in program space. These vectors are soft Ð meaning that the processor, when taking the trap, loads the program counter (PC) with the trap address and executes the code at the vector location. Four words are reserved at each vector location to accommodate a delayed branch instruction, either two 1-word instructions or one 2-word instruction, which allows branching to the appropriate interrupt service routine with minimal overhead.

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However, these vectors can be remapped to the beginning of any 128-word page in program space after device reset. This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate 128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new 128-word page.

NOTE:The hardware reset (RS) vector cannot be remapped because a hardware reset loads the IPTR with 1s. Therefore, the reset vector is always fetched at location FF80h in program space.

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13

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

extended program memory

The '5409 CPU uses a paged extended memory scheme in program space to allow access of up to 8M program memory locations. In order to implement this scheme, the '5409 includes several features that are also present on the '548/'549 devices:

Twenty-three address lines, instead of sixteen

An extra memory-mapped register, the XPC register defines the page selection. This register is memory-mapped into data space to address 001Eh. At a hardware reset, the XPC is initialized to 0.

Six extra instructions for addressing extended program space. These six instructions affect the XPC.

±FB[D] pmad (23 bits) ± Far branch

±FBACC[D] Accu[22:0] ± Far branch to the location specified by the value in accumulator A or accumulator B

±FCALL[D] pmad (23 bits) ± Far call

±FCALA[D] Accu[22:0] ± Far call to the location specified by the value in accumulator A or accumulator B

±FRET[D] ± Far return

±FRETE[D] ± Far return with interrupts enabled

In addition to these new instructions, two '54x instructions are extended to use 23 bits in the '5409:

±READA data_memory (using 23-bit accumulator address)

±WRITA data_memory (using 23-bit accumulator address)

All other instructions, software interrupts, and hardware interrupts do not modify the XPC register and access only memory within the current page.

Program memory in the '5409 is organized into 127 pages that are each 64K in length, as shown in Figure 2.

00 0000		1 0000		2 0000		. . .	7F 0000
	Page 0		Page 1		Page 2			Page 127
	64K²		Lower		Lower			Lower
			32K³		32K³			32K³
			External		External			External
		1 7FFF		2 7FFF		. . .	7F 7FFF
		1 8000		2 8000		. . .	7F 8000
			Page 1		Page 2			Page 127
			Upper		Upper			Upper
			32K		32K			32K
			External		External			External
0 FFFF		1 FFFF		2 FFFF		. . .	7F FFFF

² Refer to Figure 1. 5409 Memory Map.

³The Lower 32K words of pages 1 through 126 are available only when the OVLY bit is cleared to 0. If the OVLY bit is set to 1, the on-chip RAM is mapped to the lower 32K words of all program space pages.

Figure 2. Extended Program Memory

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TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

on-chip peripherals

The '5409 device has the following peripherals:

Software-programmable wait-state generator with programmable bank-switching wait states

An enhanced 8-bit host-port interface (HPI8/16) with 16-bit data/addressing

Three multichannel buffered serial ports (McBSPs)

One hardware timer

A clock generator with a phase-locked loop (PLL)

A direct memory access (DMA) controller

software-programmable wait-state generator

The software wait-state generator of the '5409 is similar to that of the '5410 and it can extend external bus cycles by up to fourteen machine cycles. Devices that require more than fourteen wait states can be interfaced using the hardware READY line. When all external accesses are configured for zero wait states, the internal clocks to the wait-state generator are automatically disabled. Disabling the wait-state generator clocks reduces the power consumption of the '5409.

The software wait-state register (SWWSR) controls the operation of the wait-state generator. The 14 LSBs of the SWWSR specify the number of wait states (0 to 7) to be inserted for external memory accesses to five separate address ranges. This allows a different number of wait states for each of the five address ranges. Additionally, the software wait-state multiplier (SWSM) bit of the system configuration register (SCR) defines a multiplication factor of 1 or 2 for the number of wait states. At reset, the wait-state generator is initialized to provide seven wait states on all external memory accesses. The SWWSR bit fields are shown in Figure 3 and described in Table 2.

15	14	12	11	9	8	6	5	3	2	0
XPA		I/O		Data	Data		Program			Program
R/W-0		R/W-111		R/W-111	R/W-111			R/W-111		R/W-111

LEGEND: R = Read, W = Write

Figure 3. Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

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TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

software-programmable wait-state generator (continued)

			Table 2. Software Wait-State Register (SWWSR) Bit Fields
		BIT	RESET	FUNCTION
	NO.	NAME	VALUE
	15	XPA	0	Extended program address control bit. XPA is used in conjunction with the program space fields
				(bits 0 through 5) to select the address range for program space wait states.
				I/O space. The field value (0±7) corresponds to the base number of wait states for I/O space accesses
	14±12	I/O	1	within addresses 0000±FFFFh. The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for
				the base number of wait states.
				Upper data space. The field value (0±7) corresponds to the base number of wait states for external
	11±9	Data	1	data space accesses within addresses 8000±FFFFh. The SWSM bit of the SWCR defines a
				multiplication factor of 1 or 2 for the base number of wait states.
				Lower data space. The field value (0±7) corresponds to the base number of wait states for external
	8±6	Data	1	data space accesses within addresses 0000±7FFFh. The SWSM bit of the SWCR defines a
				multiplication factor of 1 or 2 for the base number of wait states.
				Upper program space. The field value (0±7) corresponds to the base number of wait states for external
				program space accesses within the following addresses:
	5±3	Program	1	- XPA = 0: x8000 ± xFFFFh
				- XPA = 1: The upper program space bit field has no effect on wait states.
				The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait
				states.
				Program space. The field value (0±7) corresponds to the base number of wait states for external
				program space accesses within the following addresses:
	2±0	Program	1	- XPA = 0: x0000±x7FFFh
				- XPA = 1: 00000±FFFFFh
				The SWSM bit of the SWCR defines a multiplication factor of 1 or 2 for the base number of wait
				states.

The software wait-state multiplier bit of the software wait-state configuration register is used to extend the base number of wait states selected by the SWWSR. The SWCR bit fields are shown in Figure 4 and described in Table 3.

			15		1	0
					Reserved	SWSM
					R/W-0	R/W-0
	LEGEND: R = Read, W = Write
	Figure 4. Software Wait-State Configuration Register (SWCR) [MMR Address 002Bh]
			Table 3. Software Wait-State Configuration Register (SWCR) Bit Fields
	PIN			RESET	FUNCTION
NO.	NAME			VALUE
15±1	Reserved			0	These bits are reserved and are unaffected by writes.
					Software wait-state multiplier. Used to multiply the number of wait states defined in the SWWSR by a factor
					of 1 or 2.
0	SWSM			0	- SWSM = 0: wait-state base values are unchanged (multiplied by 1).
					- SWSM = 1: wait-state base values are multiplied by 2 for a maximum of 14 wait states.

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TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

programmable bank-switching wait states

The programmable bank-switching logic of the '5409 is functionally equivalent to that of the '548/'549 devices. This feature automatically inserts one cycle when accesses cross memory-bank boundaries within program or data memory space. A bank-switching wait state can also be automatically inserted when accesses cross the data space boundary into program space.

The bank-switching control register (BSCR) defines the bank size for bank-switching wait-states. Figure 5 shows the BSCR and its bits are described in Table 4.

15

12

11

10

3

2

1

0

BNKCMP

PS-DS

Reserved

HBH

BH

EXIO

R/W-1111

R/W-1

R-0

R/W-0

R/W-0

R/W-0

LEGEND: R = Read, W = Write

Figure 5. Bank-Switching Control Register (BSCR) [MMR Address 0029h]

Table 4. Bank-Switching Control Register Fields

BIT

RESET

FUNCTION

NO.

NAME

VALUE

Bank compare. BNKCMP determines the external memory-bank size. BNKCMP is used to mask the four

15±12

BNKCMP

1111

MSBs of an address. For example, if BNKCMP = 1111b, the four MSBs (bits 12±15) are compared, resulting

in a bank size of 4K words. Bank sizes of 4K words to 64K words are allowed.

Program read ± data read access. PS-DS inserts an extra cycle between consecutive accesses of program

11

PS-DS

1

read and data read or data read and program read.

PS-DS = 0

No extra cycles are inserted by this feature.

PS-DS = 1

One extra cycle is inserted between consecutive data and program reads.

10±3

Reserved

0

These bits are reserved and are unaffected by writes.

HPI bus holder. HBH controls the HPI bus holder feature. HBH is cleared to 0 at reset.

8-bit Mode

HBH = 0

The bus holder is disabled for the HPI data bus (HD[7:0]).

HBH = 1

The bus holders are enabled on HD[7:0]. When not driven, the HPI data bus (HD[7:0]) is held

in the previous logic level.

2

HBH

0

HPI bus holder. HBH controls the HPI bus holder feature. HBH is cleared to 0 at reset.

16-bit Mode

HBH = 0

The bus holder is disabled for the HPI address bus (HA[15:0]). The HPI GPIO pins (HD[7:0])

are held in the previous logic level.

HBH = 1

The bus holders are enabled on HA[15:0]. When not driven, the HPI address bus (A[15:0])

and HPI GPIO pins (HD[7:0]) are held in the previous logic level.

Bus holder. BH controls the data bus holder feature. BH is cleared to 0 at reset.

1

BH

0

BH = 0

The bus holder is disabled.

BH = 1

The bus holder is enabled. When not driven, the data bus (D[15:0]) is held in the previous

logic level.

External bus interface off. The EXIO bit controls the external bus-off function.

EXIO = 0

The external bus interface functions as usual.

0

EXIO

0

EXIO = 1

The address bus, data bus, and control signals become inactive after completing the current

bus cycle. Note that the DROM, MP/MC, and OVLY bits in the PMST and the HM bit of ST1

cannot be modified when the interface is disabled.

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17

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

parallel I/O ports

The '5409 CPU has a total of 64K I/O ports. These ports can be addressed by the PORTR instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The '5409 can interface easily with external devices through the I/O ports while requiring minimal off-chip address-decoding circuits.

enhanced 8-bit host-port interface (HPI8/16)

The '5409 host-port interface, also referred to as the HPI8/16, is an enhanced version of the standard 8-bit HPI found on earlier '54x DSPs ('542, '545, '548, and '549). The HPI8/16 is an 8-bit parallel port for interprocessor communication. The features of the HPI8/16 include:

Standard features:

Sequential transfers (with autoincrement) or random-access transfers

Host interrupt and '54x interrupt capability

Multiple data strobes and control pins for interface flexibility

Enhanced features of the '5409 HPI8/16:

Access to entire on-chip RAM through DMA bus

Capability to continue transferring during emulation stop

Capability to transfer 16-bit address and 16-bit data (non-multiplexed mode)

The HPI8/16 functions as a slave and enables the host processor to access the on-chip memory of the '5409. A major enhancement to the '5409 HPI over previous versions is that it allows host access to the entire on-chip memory range of the DSP. The HPI8/16 does not have access to external memory. The host and the DSP both have access to the on-chip RAM at all times and host accesses are always synchronized to the DSP clock. If the host and the DSP contend for access to the same location, the host has priority, and the DSP waits for one HPI8/16 cycle. Note that since host accesses are always synchronized to the '5409 clock, an active input clock (CLKIN) is required for HPI8/16 accesses during IDLE states, and host accesses are not allowed while the '5409 reset pin is asserted.

0000h

Reserved

005Fh

0060h

Scratch-Pad

RAM

007Fh

0080h

On-Chip RAM

(32K x 16 Bits)

7FFFh

8000h

Reserved

FFFFh

Figure 6. '5409 HPI Memory Map

standard 8-bit mode

The HPI8/16 interface consists of an 8-bit bidirectional data bus and various control signals. Sixteen-bit transfers are accomplished in two parts with the HBIL input designating high or low byte. The host communicates with the HPI8 through three dedicated registers Ð HPI address register (HPIA), HPI data register (HPID), and an HPI control register (HPIC). The HPIA and HPID registers are only accessible by the host, and the HPIC register is accessible by both the host and the '5409. If the HPI is disabled (HPIENA = 0) or in HPI16 mode (HPI16 = 1), the 8-bit bidirectional data pins HD0±HD7 can be used as general-purpose input/output (GPIO).

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TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

16-bit nonmultiplexed mode

In nonmultiplexed mode, a host with separate address/data buses can access the HPI16 data register (HPID) via the HD 16-bit bidirectional data bus, and the address register (HPIA) via the 16-bit HA address bus, external address and data pins, A0±A15 and D0±D15, respectively. The host initiates an access with the strobe signals (HDS1, HDS2, HCS) and controls the direction of the access with the HR/W signal. The HPI16 can stall host accesses via the HRDY signal. Note that the HPIC register is not available in nonmultiplexed mode since there are no HCNTL signals available. All host accesses initiate a DMA read or write access. The HPI16 nonmultiplexed mode does not support host-to-DSP and DSP-to-host interrupts. When the HPI is disabled or in HPI16 mode, HD0±HD7 can be configured as general-purpose input/output (GPIO). The HPI16 pin is sampled at RESET. The HPI16 pin should never be changed while the device RESET is HIGH.

host bus holder configuration

The '5409 has two bus holder control bits, BH (BSCR[1]) and HBH (BSCR[2]), to control the bus keepers of the address bus (A[15±0]), data bus (D[15±0]) and the HPI data bus (HD[7±0]). The bus keeper enabling/disabling is described in Table 5.

Table 5. Bus Holder Control Bits

HPI16 pin	BH	HBH	D[15±0]	A[15±0]	HD[7±0]
0	0	0	OFF	OFF	OFF
0	0	1	OFF	OFF	ON
0	1	0	ON	OFF	OFF
0	1	1	ON	OFF	ON
1	0	0	OFF	OFF	ON
1	0	1	OFF	ON	ON
1	1	0	ON	OFF	ON
1	1	1	ON	ON	ON

The HPI bus holders are activated via the HBH bit in the Bank Switch Control Register (BSCR). The HBH bit can control bus holder behavior for both the 8-bit and 16-bit modes. In the 8-bit mode, the HBH bit controls the bus holders on the host data pins HD7±HD0. When HBH = 1, the host data bus holders are active. When HBH = 0 the host data bus holders are inactive. In the 16-bit nonmultiplexed mode, the bus holders for pins HD7±HD0 are always active; however, the HBH bit controls the host address pins A15±A0. When HBH = 1, the host address bus holders are active. When HBH = 0, the host address bus holders are inactive.

operation during IDLE2

The HPI can continue to operate during IDLE1 or IDLE2 by using special clock management logic that turns on relevant clocks to perform a synchronous memory access, and then turns the clocks back off to save power. The DSP CPU does not wake up from the IDLE mode during this process.

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19

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

multichannel buffered serial ports (McBSPs)

The '5409 device has three high-speed, full-duplex multichannel buffered serial ports (McBSPs) that allow direct interface to other 'C54x/'LC54x devices, codecs, and other devices in a system. The McBSPs are based on the standard serial port interface found on other '54x devices. Like its predecessors, the McBSP provides:

Full-duplex communication

Double-buffer data registers, which allow a continuous data stream

Independent framing and clocking for receive and transmit

In addition, the McBSP has the following capabilities:

Direct interface to:

±T1/E1 framers

±MVIP switching-compatible and ST-BUS compliant devices

±IOM-2 compliant devices

±AC97-compliant devices

±Serial peripheral interface (SPIt) devices

Multichannel transmit and receive of up to 32 channels in a 128 channel stream.

A wide selection of data sizes including 8, 12, 16, 20, 24, or 32 bits

-law and A-law companding

Programmable polarity for both frame synchronization and data clocks

Programmable internal clock and frame generation

For detailed information on the standard features of the McBSP, refer to the TMS320C54x DSP Enhanced Peripherals Reference Set, literature number SPRU302.

Although the BCLKS pin is not available on the '5409 PGE and GGU packages, the '5409 is capable of synchronization to external clock sources. BCLKX or BCLKR can be used by the sample rate generator for external synchronization. The sample rate clock mode extended (SCLKME) bit field is located in the PCR to accommodate this option.

15	14		13	12	11	10	9	8
Reserved			XIOEN	RIOEN	FSXM	FSRM	CLKXM	CLKRM
	RW		RW	RW	RW	RW	RW	RW
7	6		5	4	3	2	1	0
SCLKME		CLKS STAT	DX STAT	DR STAT	FSXP	FSRP	CLKXP	CLKRP
RW		RW	RW	RW	RW	RW	RW	RW

LEGEND: R = Read, W = Write

Figure 7. Pin Control Register (PCR)

SPI is a trademark of Motorola Inc.

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TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

multichannel buffered serial ports (McBSPs) (continued)

Table 6. Pin Control Register (PCR) Bit Field Description

BIT	NAME		FUNCTION
15 ± 14	Reserved	Reserved. Pins are not used.
		Transmit/Receive general-purpose I/O mode ONLY when
					XRST=0 in the SPCR(1/2)
13	XIOEN	XIOEN = 0	DX pin is not a general-purpose output. FSX and CLKX are not general-purpose I/Os.
		XIOEN = 1	DX pin is a general-purpose output. FSX and CLKX are general-purpose I/Os. These serial port
			pins do not perform serial port operations.
		Transmit/Receive general-purpose I/O mode ONLY when
				RRST=0 in the SPCR(1/2)
		RIOEN = 0	DR and CLKS pins are not general-purpose inputs. FSR and CLKR are not general-purpose
12	RIOEN		I/Os.
		RIOEN = 1	DR and CLKS pins are general-purpose inputs. FSR and CLKR are general-purpose I/Os.
			These serial port pins do not perform serial port operations. The CLKS pin is affected by a
			combination of RRST and RIOEN signals of the receiver.
		Transmit frame synchronization mode
11	FSXM	FSRM = 0	Frame synchronization signal derived from an external source.
		FSRM = 1	Frame synchronization is determined by the sample rate generator frame synchronization mode
			bit (FSGM) in the SRGR2.
		Receive frame synchronization mode
10	FSRM	FSRM = 0	Frame synchronization pulses generated by an external device. FSR is an input pin.
		FSRM = 1	Frame synchronization generated internally by the sample rate generator. FSR is an output pin
			except when GSYNC=1 in the SRGR.
		Receiver clock mode
		Case 1: Digital loop-back mode is not set (DLB=0) in SPCR1.
		CLKRM = 0	Receive clock (CLKR) is an input pin driven by an external clock.
		CLKRM= 1	CLKR is an output pin and is driven by the internal sample rate generator
9	CLKRM
		Case 2: Digital loop-back mode set (DLB=1) in SPCR1
		CLKRM = 0	Receive clock (Not the CLKR pin) is driven by transmit clock (CLKX), which is based on CLKXM
			bit in the PCR. CLKR pin is in high-impedance mode.
		CLKRM= 1	CLKR is an output pin and is driven by the transmit clock. The transmit clock is derived based
			on the CLKXM bit in the PCR.
		Transmitter clock mode
		CLKXM = 0	Receiver/transmitter clock is driven by an external clock with CLK(R/X) as an input pin
		CLKXM= 1	CLK(R/X) is an output pin and is driven by the internal sample rate generator
8	CLKXM	During SPI mode (CLKSTP is a non-zero value):
		CLKXM = 0	McBSP is a slave and clock (CLKX) is driven by the SPI master in the system. CLKR is
			internally driven by CLKX.
		CLKXM= 1	McBSP is a master and generates the clock (CLKX) to drive its receive clock (CLKR) and the
			shift clock of the SPI-compliant slaves in the system.

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21

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

multichannel buffered serial ports (McBSPs) (continued)

		Table 6. Pin Control Register (PCR) Bit Field Description (Continued)
	BIT	NAME		FUNCTION
			Sample rate clock mode extended
	7	SCLKME	SCLKME = 0 External clock via CLKS or CPU clock is used as a reference by the sample rate generator.
			SCLKME = 1 External clock via CLKR or CLKX clock is used as a reference by the sample rate generator.
	6	CLKS STAT	CLKS pin status. CLKS STAT reflects value on CLKS pin when selected as a general-purpose input.
	5	DX STAT	DX pin status. DX STAT reflects value on DX pin when it is selected as a general-purpose output.
	4	DR STAT	DR pin status. DR STAT reflects value on DR pin when it is selected as a general-purpose input.
			Receive/Transmit frame synchronization polarity.
	3 ± 2	FSXP
		FSRP	FS(R/X)P = 0	Frame synchronization pulse FS(R/X) is active high
			FS(R/X)P = 1 Frame synchronization pulse FS(R/X) is active low
			Transmit clock polarity
	1	CLKXP	CLKXP = 0	Transmit data sampled on rising edge of CLKR
			CLKXP = 1	Transmit data sampled on falling edge of CLKR
			Receive clock polarity
	0	CLKRP	CLKRP = 0	Receive data sampled on falling edge of CLKR
			CLKRP = 1	Receive data sampled on rising edge of CLKR

The '5409 sample rate generator has four clock input options that are only available when both the PCR and SRGR2 are used. Table 7 shows the sample rate generator clock input options.

Table 7. Sample Rate Generator Clock Input Options

				MODE				SCLKME				CLKSM
								(PCR.7)				(SRGR2.13)
				CLKS pin					0			0
				CPU					0			1
				CLKR pin					1			0
				CLKX pin					1			1
15	14	13		12		11	10	9	8	7	6	5	4	3	2	1	0
GSYNC	CLKSP	CLKSM		FSGM								FPER
RW	RW	RW		RW								RW

LEGEND: R = Read, W = Write

Figure 8. Sample Rate Generator Register 2 (SRGR2)

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TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

multichannel buffered serial ports (McBSPs) (continued)

Table 8. Sample Rate Generator Register 2 (SRGR2) Bit Field Descriptions

BIT	NAME	FUNCTION
		Sample rate generator clock synchronization. Only used when the external clock (CLKS) drives the sample rate
		generator clock (CLKSM=0)
15	GSYNC	GSYNC = 0	The sample rate generator clock (CLKG) is free-running.
		GSYNC = 1	The sample rate generator clock (CLKG) is running. But CLKG is resynchronized and frame sync
			signal (FSG) is generated only after detecting the receive frame synchronization signal (FSR). Also,
			frame period (FPER) is a don't care because the period is dictated by the external frame sync pulse.
		CLKS polarity clock edge select. Only used when the external clock (CLKS) drives the sample rate generator clock
		(CLKSM=0).
14	CLKSP
		CLKSP = 0	Rising edge of CLKS generates CLKG and FSG.
		CLKSP = 1	Falling edge of CLKS generates CLKG and FSG.
		McBSP sample rate generator clock mode
		SCLKME = 0	CLKSM = 0	Sample rate generator clock derived from the CLKS pin
13	CLKSM	(in PCR)	CLKSM = 1	Sample rate generator clock derived from CPU clock
		SCLKME = 1	CLKSM = 0	Sample rate generator clock derived from CLKR pin
		(in PCR)	CLKSM = 1	Sample rate generator clock derived from CLKX pin
		Sample rate generator transmit frame synchronization mode. Used when FSXM=1 in the PCR.
12	FSGM	FSGM = 0	Transmit frame sync signal (FSX) due to DXR(1/2) copy
		FSGN = 1	Transmit frame sync signal driven by the sample rate generator frame sync signal (FSG)
11 ± 0	FPER	Frame period. This determines when the next frame sycn signal should become active. Range: up to 212;
		1 to 4096 CLKG periods.

hardware timer

The '5409 device features one 16-bit timing circuit with a 4-bit prescaler. The main counter of each timer is decremented by one every CLKOUT cycle. Each time the counter decrements to 0, a timer interrupt is generated. The timer can be stopped, restarted, reset, or disabled by specific control bits.

clock generator

The clock generator provides clocks to the '5409 device, and consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator requires a reference clock input, which can be provided by using a crystal resonator with the internal oscillator, or from an external clock source. The reference clock input is then divided by two (DIV mode) to generate clocks for the '5409 device, or the PLL circuit can be used (PLL mode) to generate the device clock by multiplying the reference clock frequency by a scale factor, allowing use of a clock source with a lower frequency than that of the CPU.The PLL is an adaptive circuit that, once synchronized, locks onto and tracks an input clock signal.

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23

TMS320VC5409

FIXED-POINT DIGITAL SIGNAL PROCESSOR

SPRS082C ± APRIL 1999 ± REVISED MARCH 2000

clock generator (continued)

When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. Then, other internal clock circuitry allows the synthesis of new clock frequencies for use as master clock for the '5409 device.

This clock generator allows system designers to select the clock source. The sources that drive the clock generator are:

A crystal resonator circuit. The crystal resonator circuit is connected across the X1 and X2/CLKIN pins of the '5409 to enable the internal oscillator.

An external clock. The external clock source is directly connected to the X2/CLKIN pin, and X1 is left unconnected.

The software-programmable PLL features a high level of flexibility, and includes a clock scaler that provides various clock multiplier ratios, capability to directly enable and disable the PLL, and a PLL lock timer that can be used to delay switching to PLL clocking mode of the device until lock is achieved. Devices that have a built-in software-programmable PLL can be configured in one of two clock modes:

PLL mode. The input clock (X2/CLKIN) is multiplied by 1 of 31 possible ratios. These ratios are achieved using the PLL circuitry.

DIV (divider) mode. The input clock is divided by 2 or 4. Note that when DIV mode is used, the PLL can be completely disabled in order to minimize power dissipation.

The software-programmable PLL is controlled using the 16-bit memory-mapped (address 0058h) clock mode register (CLKMD). The CLKMD register is used to define the clock configuration of the PLL clock module. Upon reset, the CLKMD register is initialized with a predetermined value dependent only upon the state of the CLKMD1 ± CLKMD3 pins as shown in Table 9.

Table 9. Clock Mode Settings at Reset

	CLKMD1	CLKMD2	CLKMD3	CLKMD	CLOCK MODE
				RESET VALUE
	0	0	0	E007h	PLL x 15
	0	0	1	9007h	PLL x 10
	0	1	0	4007h	PLL x 5
	1	0	0	1007h	PLL x 2
	1	1	0	F007h	PLL x 1
	1	1	1	0000h	1/2 (PLL disabled)
	1	0	1	F000h	1/4 (PLL disabled)
	0	1	1	Ð	Reserved

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