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TLV5624 |
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2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG |
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CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN |
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SLAS235 ± JULY 1999 |
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features |
D OR DGK PACKAGE |
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(TOP VIEW) |
D D D
D
D D
8-Bit Voltage Output DAC |
DIN |
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VDD |
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Programmable Internal Reference |
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1 |
8 |
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Programmable Settling Time: |
SCLK |
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2 |
7 |
OUT |
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1 μs in Fast Mode, |
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CS |
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3 |
6 |
REF |
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FS |
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4 |
5 |
AGND |
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3.5 μs in Slow Mode |
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Compatible With TMS320 and SPI Serial |
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Ports |
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Differential Nonlinearity . . . <0.2 LSB Typ |
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Monotonic Over Temperature |
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applications
DDigital Servo Control Loops
DDigital Offset and Gain Adjustment
DIndustrial Process Control
DMachine and Motion Control Devices
DMass Storage Devices
description
The TLV5624 is a 8-bit voltage output DAC with a flexible 4-wire serial interface. The serial interface allows glueless interface to TMS320 and SPI , QSPI , and Microwire serial ports. It is programmed with a 16-bit serial string containing 4 control and 8 data bits.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The programmable settling time of the DAC allows the designer to optimize speed vs power dissipation. With its on-chip programmable precision voltage reference, the TLV5624 simplifies overall system design.
Because of its ability to source up to 1 mA, the reference can also be used as a system reference. Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in an 8-pin SOIC and 8-pin MSOP package to reduce board space in standard commercial and industrial temperature ranges.
AVAILABLE OPTIONS
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PACKAGE |
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TA |
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SOIC |
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MSOP |
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(D) |
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(DGK) |
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0°C to 70°C |
TLV5624CD |
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TLV5624CDGK |
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± 40°C to 85°C |
TLV5624ID |
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TLV5624IDGK |
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
TLV5624
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235 ± JULY 1999
functional block diagram
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REF |
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PGA With |
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Output Enable |
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Voltage |
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Bandgap |
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Power |
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Power-On |
and Speed |
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Reset |
Control |
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2 |
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2 |
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2-Bit |
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Control |
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DIN |
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Latch |
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Serial |
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SCLK |
Interface |
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CS |
and |
8 |
8 |
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Control |
8-Bit |
x2 |
OUT |
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DAC |
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FS |
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Latch |
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Terminal Functions |
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TERMINAL |
I/O/P |
DESCRIPTION |
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NAME |
NO. |
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AGND |
5 |
P |
Ground |
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3 |
I |
Chip select. Digital input active low, used to enable/disable inputs |
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CS |
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DIN |
1 |
I |
Digital serial data input |
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FS |
4 |
I |
Frame sync input |
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OUT |
7 |
O |
DAC A analog voltage output |
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REF |
6 |
I/O |
Analog reference voltage input/output |
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SCLK |
2 |
I |
Digital serial clock input |
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VDD |
8 |
P |
Positive power supply |
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TLV5624 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235 ± JULY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²
Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . 7 |
V |
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
± 0.3 V to VDD + 0.3 |
V |
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
± 0.3 V to VDD + 0.3 |
V |
Operating free-air temperature range, TA: TLV5624C . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . 0°C to 70°C |
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TLV5624I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . ±40°C to 85°C |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . ±65°C to 150°C |
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Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . 260°C |
²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
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MIN |
NOM |
MAX |
UNIT |
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Supply voltage, VDD |
VDD = 5 V |
4.5 |
5 |
5.5 |
V |
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VDD = 3 V |
2.7 |
3 |
3.3 |
V |
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Power on reset, POR |
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0.55 |
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2 |
V |
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High-level digital input voltage, VIH |
VDD = 2.7 V to 5.5 V |
2 |
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V |
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Low-level digital input voltage, VIL |
VDD = 2.7 V to 5.5 V |
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0.8 |
V |
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Reference voltage, Vref to REF terminal |
VDD = 5 V (see Note 1) |
AGND |
2.048 |
VDD ±1.5 |
V |
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Reference voltage, Vref to REF terminal |
VDD = 3 V (see Note 1) |
AGND |
1.024 |
VDD ± 1.5 |
V |
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Load resistance, RL |
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2 |
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kΩ |
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Load capacitance, CL |
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100 |
pF |
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Clock frequency, fCLK |
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20 |
MHz |
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Operating free-air temperature, TA |
TLV5624C |
0 |
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70 |
°C |
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TLV5624I |
±40 |
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85 |
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NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD±0.4 V)/2 causes clipping of the transfer function. The output buffer of the internal reference must be disabled, if an external reference is used.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
TLV5624
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235 ± JULY 1999
electrical characteristics over recommended operating conditions (unless otherwise noted)
power supply
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PARAMETER |
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TEST CONDITIONS |
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MIN |
TYP |
MAX |
UNIT |
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No load, |
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Fast |
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2.3 |
3.3 |
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IDD |
Power supply current |
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All inputs = AGND or VDD, |
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mA |
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Slow |
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1.5 |
1.9 |
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DAC latch = 0x800 |
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Power down supply current |
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See Figure 8 |
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0.01 |
10 |
mA |
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PSRR |
Power supply rejection ratio |
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Zero scale, |
See Note 2 |
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±65 |
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dB |
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Full scale, |
See Note 3 |
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±65 |
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NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: |
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PSRR = 20 log [(EZS(VDDmax) ± EZS(VDDmin))/VDDmax] |
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3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: |
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PSRR = 20 log [(EG(VDDmax) ± EG(VDDmin))/VDDmax] |
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static DAC specifications |
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PARAMETER |
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TEST CONDITIONS |
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MIN |
TYP |
MAX |
UNIT |
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Resolution |
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8 |
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bits |
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INL |
Integral nonlinearity, end point adjusted |
See Note 4 |
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± 0.3 |
± 0.5 |
LSB |
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DNL |
Differential nonlinearity |
See Note 5 |
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± 0.07 |
± 0.2 |
LSB |
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EZS |
Zero-scale error (offset error at zero scale) |
See Note 6 |
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±10 |
mV |
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EZS TC |
Zero-scale-error temperature coefficient |
See Note 7 |
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10 |
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ppm/°C |
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EG |
Gain error |
See Note 8 |
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± 0.6 |
% full |
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scale V |
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EG TC |
Gain error temperature coefficient |
See Note 9 |
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10 |
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ppm/°C |
NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.
5.The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
6.Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
7.Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) ± EZS (Tmin)]/Vref × 106/(Tmax ± Tmin).
8.Gain error is the deviation from the ideal output (2Vref ± 1 LSB) with an output load of 10 kW excluding the effects of the zero-error.
9.Gain temperature coefficient is given by: EG TC = [EG(Tmax) ± EG (Tmin)]/Vref × 106/(Tmax ± Tmin).
output specifications
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PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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VO |
Output voltage |
RL = 10 kW |
0 |
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VDD±0.4 |
V |
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Output load regulation accuracy |
VO = 4.096 V, 2.048 V RL = 2 kW |
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± 0.10 |
± 0.25 |
% full |
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scale V |
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reference pin configured as output (REF)
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PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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Vref(OUTL) |
Low reference voltage |
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1.003 |
1.024 |
1.045 |
V |
Vref(OUTH) |
High reference voltage |
VDD > 4.75 V |
2.027 |
2.048 |
2.069 |
V |
Iref(source) |
Output source current |
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1 |
mA |
Iref(sink) |
Output sink current |
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±1 |
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mA |
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Load capacitance |
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100 |
pF |
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PSRR |
Power supply rejection ratio |
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±65 |
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dB |
4 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TLV5624 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235 ± JULY 1999
electrical characteristics over recommended operating conditions (unless otherwise noted) (Continued)
reference pin configured as input (REF)
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PARAMETER |
TEST CONDITIONS |
MIN TYP |
MAX |
UNIT |
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VI |
Input voltage |
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0 |
VDD±1.5 |
V |
RI |
Input resistance |
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10 |
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MΩ |
CI |
Input capacitance |
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5 |
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pF |
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Reference input bandwidth |
REF = 0.2 Vpp + 1.024 V dc |
Fast |
1.3 |
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MHz |
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Slow |
525 |
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kHz |
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Reference feedthrough |
REF = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) |
± 80 |
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dB |
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
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PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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IIH |
High-level digital input current |
VI = VDD |
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1 |
μA |
IIL |
Low-level digital input current |
VI = 0 V |
±1 |
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μA |
Ci |
Input capacitance |
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8 |
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pF |
analog output dynamic performance
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PARAMETER |
TEST CONDITIONS |
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MIN |
TYP |
MAX |
UNIT |
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ts(FS) |
Output settling time, full scale |
RL = 10 kΩ, |
CL = 100 pF, |
Fast |
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1 |
3 |
μs |
See Note 11 |
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Slow |
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3.5 |
7 |
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ts(CC) |
Output settling time, code to code |
RL = 10 kΩ, |
CL = 100 pF, |
Fast |
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0.5 |
1.5 |
μs |
See Note 12 |
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Slow |
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1 |
2 |
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SR |
Slew rate |
RL = 10 kΩ, |
CL = 100 pF, |
Fast |
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8 |
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V/μs |
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Slow |
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1.5 |
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See Note 13 |
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Glitch energy |
DIN = 0 to 1, |
fCLK = 100 kHz, |
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5 |
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nV±S |
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CS = VDD |
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SNR |
Signal-to-noise ratio |
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53 |
57 |
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S/(N+D) |
Signal-to-noise + distortion |
fs = 480 kSPS, |
fout = 1 kHz, |
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48 |
47 |
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dB |
THD |
Total harmonic distortion |
RL = 10 kΩ, |
CL = 100 pF |
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±50 |
±48 |
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Spurious free dynamic range |
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50 |
62 |
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NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFDFand 0xFDF to 0x020 respectively. Not tested, assured by design.
12.Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, assured by design.
13.Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
5 |
TLV5624
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTER WITH INTERNAL REFERENCE AND POWER DOWN
SLAS235 ± JULY 1999
digital input timing requirements
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MIN NOM MAX |
UNIT |
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tsu(CS±FS) |
Setup time, |
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low before FS falling edge |
10 |
ns |
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CS |
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tsu(FS-CK) |
Setup time, FS low before first negative SCLK edge |
8 |
ns |
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tsu(C16-FS) |
Setup time, 16th negative SCLK edge after FS low on which bit D0 is sampled before rising |
10 |
ns |
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edge of FS |
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Setup time, 16th positive SCLK edge (first positive after D0 is sampled) before |
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rising |
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CS |
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t |
edge. If FS is used instead of 16th positive edge to update DAC, then setup time between |
10 |
ns |
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su(C16-CS) |
FS rising edge and CS rising edge. |
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twH |
SCLK pulse duration high |
25 |
ns |
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twL |
SCLK pulse duration low |
25 |
ns |
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tsu(D) |
Setup time, data ready before SCLK falling edge |
8 |
ns |
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tH(D) |
Hold time, data held valid after SCLK falling edge |
5 |
ns |
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twH(FS) |
FS pulse duration high |
25 |
ns |
PARAMETER MEASUREMENT INFORMATION
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twL |
twH |
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SCLK |
X |
1 |
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2 |
3 |
4 |
5 |
15 |
16 |
X |
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tsu(D) th(D) |
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DIN |
X |
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D15 |
D14 |
D13 |
D12 |
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D1 |
D0 |
X |
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tsu(C16-CS) |
tsu(CS-FS) |
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CS |
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twH(FS) |
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tsu(FS-CK) |
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tsu(C16-FS) |
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FS
Figure 1. Timing Diagram
6 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |