Texas Instruments TPS2330IPWR, TPS2330IPW, TPS2330IDR, TPS2330ID, TPS2331IPWR Datasheet

TPS2330, TPS2331 SINGLE HOT SWAP POWER CONTROLLER WITH CIRCUIT BREAKER AND POWER-GOOD REPORTING

SLVS277A ± MARCH 2000± REVISED APRIL 2000

features

DSingle-Channel High-Side MOSFET Driver

DInput Voltage: 3 V to 13 V

DInrush Current Limiting With dv/dt Control

DCircuit-Breaker Control With Programmable Current Limit and Transient Timer

DPower-Good Reporting With Transient Filter

DCMOSand TTL-Compatible Enable Input

DLow 5- A Standby Supply Current . . . Max

DAvailable in 14-Pin SOIC and TSSOP Package

D±40°C to 85°C Ambient Temperature Range

DElectrostatic Discharge Protection

applications

DHot-Swap/Plug/Dock Power Management

DHot-Plug PCI, Device Bay

DElectronic Circuit Breaker

description

D OR PW PACKAGE

(TOP VIEW)

GATE			1	14				DISCH
DGND			2	13				ENABLE
TIMER			3	12			PWRGD
VREG			4	11			FAULT
VSENSE			5	10			ISET
AGND			6	9			AGND
ISENSE			7	8			IN

NOTE: Terminal 13 is active high on TPS2331.

typical application

VO

+

VIN 3 V ± 13 V

IN	ISET ISENSE GATE	DISCH
VREG		VSENSE
AGND	TPS2330	PWRGD
DGND		FAULT
ENABLE		TIMER

The TPS2330 and TPS2331 are single-channel hot-swap controllers that use external N-channel MOSFETs as high-side switches in power applications. Features of these devices, such as overcurrent protection (OCP), inrush-current control, output-power status reporting, and separation of load transients from actual load increases, are critical requirements for hot-swap applications.

The TPS2330/31 devices incorporate undervoltage lockout (UVLO) and power-good (PG) reporting to ensure the device is off at start-up and confirm the status of the output voltage rails during operation. An internal charge pump, capable of driving multiple MOSFETs, provides enough gate-drive voltage to fully enhance the N-channel MOSFETs. The charge pump controls both the rise times and fall times (dv/dt) of the MOSFETs, reducing power transients during power up/down. The circuit-breaker functionality combines the ability to sense overcurrent conditions with a timer function; this allows designs such as DSPs, that may have high peak currents during power-state transitions, to disregard transients for a programmable period.

AVAILABLE OPTIONS

	TA	HOT-SWAP CONTROLLER DESCRIPTION		PIN			PACKAGES
				COUNT	ENABLE			ENABLE
		Dual-channel with independent OCP and adjustable PG		20	TPS2300IPW			TPS2301IPW
		Dual-channel with interdependent OCP and adjustable PG		20	TPS2310IPW			TPS2311IPW
	± 40°C to 85°C	Dual-channel with independent OCP		16	TPS2320ID			TPS2321ID
					TPS2320IPW			TPS2321IPW
		Single-channel with OCP and adjustable PG		14	TPS2330ID			TPS2331ID
					TPS2330IPW			TPS2331IPW

² The packages are available left-end taped and reeled (indicated by the R suffix on the device type; e.g., TPS2331IPWR).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TPS2330, TPS2331

SINGLE HOT SWAP POWER CONTROLLER WITH

CIRCUIT BREAKER AND POWER-GOOD REPORTING

SLVS277A ± MARCH 2000± REVISED APRIL 2000

functional block diagram

IN

ISET

ISENSE GATE

DISCH

VREG	PREREG		Clamp
			dv/dt Rate
			Protection
	50 A	Circuit	Charge
			Pump
		Breaker

Pulldown FET

AGND

UVLO and

Circuit Breaker

VSENSE

Power-Up

75 A

PWRGD

DGND

20- s Deglitch

FAULT

ENABLE

Logic

50- s Deglitch

TIMER

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AGND

6,9

I

Analog ground, connects to DGND as close as possible

DGND

2

I

Digital ground

DISCH

14

O

Discharge transistor

ENABLE

13

I

Active low (TPS2330) or active high enable (TPS2331)

ENABLE/

FAULT

11

O

Overcurrent fault, open-drain output

GATE

1

O

Connects to gate of high-side MOSFET

IN

8

I

Input voltage

ISENSE

7

I

Current-sense input

ISET

10

I

Adjusts circuit-breaker threshold with resistor connected to IN

PWRGD

12

O

Open-drain output, asserted low when VSENSE voltage is less than reference.

TIMER

3

O

Adjusts circuit-breaker deglitch time

VREG

4

O

Connects to bypass capacitor, for stable operation

VSENSE

5

I

Power-good sense input

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS2330, TPS2331

SINGLE HOT SWAP POWER CONTROLLER WITH

CIRCUIT BREAKER AND POWER-GOOD REPORTING

SLVS277A ± MARCH 2000± REVISED APRIL 2000

detailed description

DISCH ± DISCH should be connected to the source of the external N-channel MOSFET transistor connected to GATE. This pin discharges the load when the MOSFET transistor is disabled. They also serve as reference-voltage connection for internal gate-voltage-clamp circuitry.

ENABLE or ENABLE ± ENABLE for TPS2330 is active low. ENABLE for TPS2331 is active high. When the controller is enabled, GATE voltage will power up to turn on the external MOSFETs. When the ENABLE pin is pulled high for TPS2330 or the ENABLE pin is pulled low for TPS2331 for more than 50 s, the gate of the MOSFET is discharged at a controlled rate by a current source, and a transistor is enabled to discharge the output bulk capacitance. In addition, the device turns on the internal regulator PREREG (see VREG) when enabled and shuts down PREREG when disabled so that total supply current is much less than 5 A.

FAULT ± FAULT is an open-drain overcurrent flag output. When an overcurrent condition is sustained long enough to charge TIMER to 0.5 V, the device latches off and pulls FAULT low.

GATE ± GATE connects to the gate of the external N-channel MOSFET transistor. When the device is enabled, internal charge-pump circuitry pulls this pin up by sourcing approximately 15 A. The turnon slew rates depend upon the capacitance present at the GATE terminal. If desired, the turnon slew rates can be further reduced by connecting capacitors between this pin and ground. These capacitors also reduce inrush current and protect the device from false overcurrent triggering during powerup. The charge-pump circuitry will generate gate-to-source voltages of 9 V±12 V across the external MOSFET transistor.

IN ± IN should be connected to the power source driving the external N-channel MOSFET transistor connected to GATE. The TPS2330/31 draws its operating current from IN, and will remain disabled until the IN power supply has been established. The device has been constructed to support 3-V, 5-V, or 12-V operation.

ISENSE, ISET ± ISENSE in combination with ISET implements overcurrent sensing for GATE. ISET sets the magnitude of the current that generates an overcurrent fault, through a external resistor connected to ISET. An internal current source draws 50 A from ISET. With a sense resistor from IN to ISENSE, which is also connected to the drain of the external MOSFET, the voltage on the sense resistor reflects the load current. An overcurrent condition is assumed to exist if ISENSE is pulled below ISET.

PWRGD ± PWRGD signals the presence of undervoltage conditions on VSENSE. The pin is an open-drain output and is pulled low during an undervoltage condition. To minimize erronous PWRGD responses from transients on the voltage rail, the voltage sense circuit incorporates a 20- s deglitch filter. When VSENSE is lower than the reference voltage (about 1.23 V), PWRGD will be active low to indicate an undervoltage condition on the power-rail voltage.

TIMER ± A capacitor on TIMER sets the time during which the power switch can be in overcurrent before turning off. When the overcurrent protection circuits sense an excessive current, a current source is enabled which charges the capacitor on TIMER. Once the voltage on TIMER reaches approximately 0.5 V, the circuit-breaker latch is set and the power switch is latched off. Power must be recycled or the ENABLE pin must be toggled to restart the controller. In high-power or high-temperature applications, a minimum 50-pF capacitor is strongly recommended from TIMER to ground, to prevent any false triggering.

VREG ± The VREG pin is the output of an internal low-dropout voltage regulator. This regulator draws current from IN. A 0.1- F ceramic capacitor should be connected between VREG and ground. VREG can be connected to IN or to a separated power supply through a low-resistance resistor. However, the voltage on VREG must be less than 5.5 V.

VSENSE ± VSENSE can be used to detect undervoltage conditions on external circuitry. If VSENSE senses a voltage below approximately 1.23 V, PWRGD is pulled low.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TPS2330, TPS2331

SINGLE HOT SWAP POWER CONTROLLER WITH

CIRCUIT BREAKER AND POWER-GOOD REPORTING

SLVS277A ± MARCH 2000± REVISED APRIL 2000

absolute maximum ratings over operating free-air temperature (unless otherwise noted)²

Input voltage range:	VI(IN), VI(ISENSE), VI(VSENSE),VI(ISET), VI(ENABLE) . . . . . . . . . . . . . .	. ±0.3 V to 15 V
Output voltage range: VO(GATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		. ±0.3 V to 30 V
	VO(DISCH), VO(PWRGD), VO(FAULT), VO(VREG), VO(TIMER) . . . . . .	. ±0.3 V to 15V
Sink current range:	IGATE, IDISCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 mA to 100 mA
	IPWRGD, ITIMER, IFAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	0 mA to 10 mA
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		±40°C to 100°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		±55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . .		. . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltages are respect to DGND.

DISSIPATION RATING TABLE

	PACKAGE	TA ≤ 25°C	DERATING FACTOR	TA = 70°C	TA = 85°C
		POWER RATING	ABOVE TA = 25°C	POWER RATING	POWER RATING
	PW-14	755 mW	10.07 mW/°C	302 mW	151 mW
	D-14	613 mW	8.18 mW/°C	245 mW	123 mW

recommended operating conditions

		MIN NOM	MAX	UNIT
Input voltage, VI	VI(IN), VI(ISENSE), VI(VSENSE), VI(ISET)	3	13	V
VREG voltage, VO(VREG), when VREG is directly connected to IN		2.95	5.5	V
Operating virtual junction temperature, TJ		±40	100	°C

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS2330, TPS2331

SINGLE HOT SWAP POWER CONTROLLER WITH

CIRCUIT BREAKER AND POWER-GOOD REPORTING

SLVS277A ± MARCH 2000± REVISED APRIL 2000

electrical characteristics over recommended operating temperature range (±40°C < TA < 85°C), 3 V ≤ VI(IN) ≤13 V (unless otherwise noted)

general

	PARAMETER		TEST CONDITIONS		MIN TYP	MAX	UNIT
II(IN)	Input current, IN	VI(ENABLE) = 5 V (TPS2331),			0.5	1	mA
		VI(ENABLE) = 0 V (TPS2330)			75	200
II(stby)	Standby current (sum of currents into IN ISENSE and ISET)	VI(ENABLE) = 0 V (TPS2331),				5	µA
		VI(ENABLE) = 5 V (TPS2330)

GATE

	PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
VG(GATE_3V)			II(GATE) = 500 nA,	VI(IN) = 3 V	9	11.5
VG(GATE_4.5V)		Gate voltage		VI(IN) = 4.5 V	10.5	14.5		V
			DISCH open
VG(GATE_10.8V)				VI(IN) = 10.8 V	16.8	21
VC(GATE)		Clamping voltage, GATE to			9	10	12	V
		DISCH
IS(GATE)		Source current, GATE	3 V ≤ VI(IN) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,		10	14	20	µA
			VI(GATE) = VI(IN) + 6 V
		Sink current, GATE	3 V ≤ VI(IN) ≤ 13.2 V, 3 V ≤ VO(VREG) ≤ 5.5 V,		50	75	100	µA
			VI(GATE) = VI(IN)
				VI(IN) = 3 V		0.5
tr(GATE)		Rise time, GATE	Cg to GND = 1 nF (see Note 2)	VI(IN) = 4.5 V		0.6		ms
				VI(IN) = 10.8 V		1
				VI(IN) = 3 V		0.1
tf(GATE)		Fall time, GATE	Cg to GND = 1 nF (see Note 2)	VI(IN) = 4.5 V		0.12		ms
				VI(IN) = 10.8 V		0.2
NOTE 2: Specified, but not production tested.

TIMER

PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VOT(TIMER) Threshold voltage, TIMER		0.4	0.5	0.6	V
Charge current, TIMER	VI(TIMER) = 0 V	35	50	65	µA
Discharge current, TIMER	VI(TIMER) = 1 V	1	2.5		mA

circuit breaker

	PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
VIT(CB)	Undervoltage voltage, circuit breaker	RISET = 1 kΩ		40	50	60	mV
IIB(ISENSE)	Input bias current, ISENSE				0.1	5	µA
	Discharge current, GATE	VO(GATE) = 4 V		400	800		mA
		VO(GATE) = 1 V		25	150
tpd(CB)	Propagation (delay) time, comparator inputs to	Cg = 50 pF,	10 mV overdrive,		1.3		µs
	gate output	(50% to 10%)	CO(timer) = 50 pF

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TPS2330, TPS2331

SINGLE HOT SWAP POWER CONTROLLER WITH

CIRCUIT BREAKER AND POWER-GOOD REPORTING

SLVS277A ± MARCH 2000± REVISED APRIL 2000

electrical characteristics over recommended operating temperature range (±40°C < TA < 85°C), 3 V ≤ VI(IN) ≤13 V (unless otherwise noted) (continued)

ENABLE, active low (TPS2330)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

High-level input voltage,

2

V

IH(ENABLE)

ENABLE

V

Low-level input voltage,

0.8

V

IL(ENABLE)

ENABLE

Input pullup resistance,

kΩ

RI(ENABLE)

See Note 3

100

200

300

ENABLE

V

increasing above stop threshold; 100

I(ENABLE)

µs

td_off(ENABLE)

Turnoff delay time, ENABLE

60

ns rise time, 20 mV overdrive (see Note 2)

V

decreasing below start threshold;

I(ENABLE)

µs

td_on(ENABLE)

Turnon delay time, ENABLE

125

100 ns fall time, 20 mV overdrive (see Note 2)

NOTES: 2. Specified, but not production tested.

1 V

3. Test IO of ENABLE at VI(ENABLE) = 1 V and 0 V, then RI(ENABLE) =

IO_0V

IO_1V

ENABLE, active high (TPS2331)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VIH(ENABLE)

High-level input voltage, ENABLE

2

V

VIL(ENABLE)

Low-level input voltage, ENABLE

0.7

V

RI(ENABLE)

Input pulldown resistance,

100

150

300

kΩ

ENABLE

td_on(ENABLE)

Turnon delay time, ENABLE

VI(ENABLE) increasing above start threshold;

85

µs

100 ns rise time, 20 mV overdrive (see Note 2)

td_off(ENABLE)

Turnoff delay time, ENABLE

VI(ENABLE) decreasing below stop threshold;

100

µs

100 ns fall time, 20 mV overdrive (see Note 2)

NOTE 2: Specified, but not production tested.

PREREG

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VREG	PREREG output voltage	4.5 ≤ VI(IN) ≤ 13 V	3.5	4.1	5.5	V
Vdrop_PREREG	PREREG dropout voltage	VI(IN) = 3 V			0.1	V

VREG UVLO

	PARAMETER	TEST CONDITIONS	MIN	TYP	MAX	UNIT
VOT(UVLOstart)	Output threshold voltage, start		2.75	2.85	2.95	V
VOT(UVLOstop)	Output threshold voltage, stop		2.65	2.78		V
Vhys(UVLO)	Hysteresis		50	75		mV
	UVLO sink current, GATE	VI(GATE) = 2 V	10			mA

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265