TPIC46L01, TPIC46L02, TPIC46L03 6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A ± NOVEMBER 1996 - REVISED SEPTEMBER 1997
D6-Channel Serial-in/Parallel-in Low-side Pre-FET Driver
DDevice Can Be Cascaded
DInternal 55-V Inductive Load Clamp and
VGS Protection Clamp for External Power FETs
DIndependent Shorted-Load/Short-to-Battery Fault Detection on All Drain Terminals
DIndependent Off-State Open-Load Fault Sense
DOver-Battery-Voltage Lockout Protection and Fault Reporting
DUnder-Battery-Voltage Lockout Protection for TPIC46L01 and TPIC46L02
DAsynchronous Open-Drain Fault Flag
DDevice Output Can be Wire-ORed with Multiple External Devices
DFault Status Returned Through Serial Output Terminal
DB PACKAGE (TOP VIEW)
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FLT |
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1 |
28 |
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VBAT |
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VCOMPEN |
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2 |
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GATE0 |
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VCOMP |
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3 |
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DRAIN0 |
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IN0 |
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GATE1 |
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IN1 |
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DRAIN1 |
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IN2 |
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DRAIN2 |
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IN3 |
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GATE2 |
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IN4 |
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GATE3 |
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IN5 |
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DRAIN3 |
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CS |
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DRAIN4 |
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SDO |
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GATE4 |
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SDI |
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12 |
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DRAIN5 |
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SCLK |
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GATE5 |
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VCC |
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GND |
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D D
Internal Global Power-on Reset of Device
High-Impedance CMOS Compatible Inputs
With Hysteresis
DTPIC46L01 and TPIC46L03 Disables the Gate Output When a Shorted-Load Fault Occurs
DTPIC46L02 Transitions the Gate Output to a Low-Duty-Cycle PWM Mode When a Shorted-Load Fault Occurs
description
The TPIC46L01, TPIC46L02, and TPIC46L03 are low-side predrivers that provide serial input interface and parallel input interface to control six external field-effect transistor(FET) power switches such as offered in the TI TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format. Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery detection. Battery overvoltage and undervoltage detection and shutdown are provided. Battery and output load faults provide real-time fault reporting to the controller. Each channel also provides inductive-voltage-transient protection for the external FET.
These devices provide control of output channels through a serial input interface or a parallel input interface. A command to enable the output from either interface enables the respective channel GATE output to the external FET. The serial input interface is recommended when the number of signals between the control device and the predriver must be minimized, and the speed of operation is not critical. In applications where the predriver must respond very quickly or asynchronously, the parallel input interface is recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A ± NOVEMBER 1996 - REVISED SEPTEMBER 1997
For serial operation, the control device must transition CS from high to low to activate the serial input interface. When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT flag is refreshed.
Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03) and shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared asynchronously to reflect the current state of the hardware. The fault must be present when CS is transitioned from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial register when CS is low. CS must be transitioned high after all of the serial data has been clocked into the device. A low-to-high transition of CS transfers the last six bits of serial data to the output buffer, puts SDO in a high-impedance state, and clears and re-enables the fault register. The TPIC46L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the controller. Serial input data flows through the device and is transferred out SDO following the fault data in cascaded configurations.
For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to the respective GATE output. SCLK or CS are not required for parallel control. A 1 on the parallel input turns the respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data interface.
The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions in the on and off states respectively. These devices offer the option of using an internally generated fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is selected by connecting VCOMPEN to GND and the external reference is selected by connecting VCOMPEN to VCC. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT as well as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel transitions into a low-duty-cycle, pulse-width-modulated (PWM) signal as long as the fault is present. Shorted-load conditions must be present for at least the shorted-load deglitch time, t(STBDG), in order to be
flagged as a fault. A fault signal is sent to FLT as well as the serial fault register bit. More detail on fault detection operation is presented in the device operation section of this data sheet.
The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no undervoltage threshold), all channels are disabled and a fault signal is sent to FLT as well as to the respective fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are re-enabled after the battery fault condition has been corrected.
These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect the FET. This clamp voltage is defined by the sum of VC and turn-on voltage of the external FET. The predriver also provides a gate-to-source voltage (VGS) clamp to protect the GATE-source terminals of the power FET from exceeding their rated voltages.
These devices provide pulldown resistors on all inputs except CS. A pullup resistor is used on CS.
2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TPIC46L01, TPIC46L02, TPIC46L03 6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A ± NOVEMBER 1996 - REVISED SEPTEMBER 1997
schematic diagram |
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8 |
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Fault Logic |
UVLO² |
OVLO |
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SDI |
Serial Register |
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SDO |
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SCLK |
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VCC |
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CS |
Parallel Register |
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8 |
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IN 0 |
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PREZ |
IN 1 |
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IN 2 |
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GND |
D |
IN 3 |
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Q |
IN 4 |
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IN 5 |
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DRAIN 0 |
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8 |
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DRAIN 1 |
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DRAIN 2 |
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DRAIN 3 |
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DRAIN 4 |
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DRAIN 5 |
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6 |
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STB and Open-Load Fault |
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Protection |
OSC |
S |
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BIAS |
B |
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Gate |
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A |
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Drive Block |
Vbg |
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VBAT |
OVLO |
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GATE 0 |
UVLO² |
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GATE 1 |
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GATE 2 |
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GATE 3 |
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GATE 4 |
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GATE 5 |
² UVLO is not in TPIC46L03 |
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FLT
VCOMPEN
VCOMP
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A ± NOVEMBER 1996 - REVISED SEPTEMBER 1997
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Terminal Functions |
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TERMINAL |
I/O |
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DESCRIPTION |
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NAME |
NO. |
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10 |
I |
Chip select. A high to low transition on the |
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enables SDO, latches fault data into the serial interface, and |
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CS |
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CS |
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refreshes the fault flag. When CS is high, the fault registers can change fault status. On the falling edge of CS, fault |
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data is latched into the serial output register and transferred using SDO and SCLK. On a low to high transition of |
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CS, serial data is latched in to the output control register. |
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DRAIN0 |
26 |
I |
FET drain inputs. DRAIN0 through DRAIN5 are used for both open-load and short-circuit fault detection at the drain |
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DRAIN1 |
24 |
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of the external FETs. They are also used for inductive transient protection. |
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DRAIN2 |
23 |
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DRAIN3 |
20 |
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DRAIN4 |
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DRAIN5 |
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1 |
O |
Fault flag. |
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is an open-drain output that provides a real-time fault flag for shorted-load/open-load/over-battery |
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FLT |
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FLT |
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voltage/under-battery voltage faults. The device can be ORed with FLT on other devices for interrupt handling. FLT |
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requires an external pullup resistor. |
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GATE0 |
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O |
Gate drive output. GATE0 through GATE5 outputs are derived from the VBAT supply. Internal clamps prevent the |
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GATE1 |
25 |
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voltages on these nodes from exceeding the VGS rating on most FETs. |
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GATE2 |
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GATE3 |
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GATE4 |
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GATE5 |
16 |
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GND |
15 |
I |
Ground and substrate |
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IN0 |
4 |
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Parallel gate driver inputs. IN0 through IN5 are real-time controls for the gate predrive circuitry. They are CMOS |
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IN1 |
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compatible with hysteresis. |
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IN2 |
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IN3 |
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IN4 |
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IN5 |
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SCLK |
13 |
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Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out of |
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SDO on the falling edge of the serial clock. |
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SDI |
12 |
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Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a |
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particular gate output on and a 0 turns it off. |
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SDO |
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O |
Serial data output. SDO is a 3-state output that transfers fault data to the controling device. It also passes serial |
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input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS is in a high |
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state. |
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VBAT |
28 |
I |
Battery supply voltage input |
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VCC |
14 |
I |
Logic supply voltage |
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VCOMPEN |
2 |
I |
Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an |
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external fault reference (1) to be used in the shortedand open-load fault detection circuitry. |
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VCOMP |
3 |
I |
Fault reference voltage. VCOMP provides an external fault reference voltage for the shortedand open-load fault |
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detection circuitry. |
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4 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TPIC46L01, TPIC46L02, TPIC46L03 6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A ± NOVEMBER 1996 - REVISED SEPTEMBER 1997
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . ±0.3 V to 7 V |
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Battery supply voltage range, VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . ±0.3 V to 60 V |
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Input voltage range,VI (at any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . ±0.3 V to 7 |
V |
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Output voltage range, VO (SDO and |
FLT) |
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . ±0.3 V to 7 |
V |
Drain-to-source input voltage, VDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . ±0.3 V to 60 |
V |
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Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . ±0.3 V to 15 |
V |
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Operating case temperature range, TC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±40°C to + 125°C |
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Thermal resistance, junction to ambient, RθJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . 112°C/W |
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Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . 150°C |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±40°C to + 150°C |
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²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
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MIN |
NOM |
MAX |
UNIT |
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Logic supply voltage, VCC |
4.5 |
5.0 |
5.5 |
V |
Battery supply voltage, VBAT |
8 |
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24 |
V |
High-level input voltage, VIH |
0.85 VCC |
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VCC |
V |
Low-level input voltage, VIL |
0 |
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0.15 VCC |
V |
Setup time, SDI high before SCLK rising edge, tsu (see Figure 5) |
10 |
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Hold time, SDI high after SCLK rising edge, th (see Figure 5) |
10 |
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Case temperature, TC |
±40 |
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125 |
°C |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
5 |
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A ± NOVEMBER 1996 - REVISED SEPTEMBER 1997
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
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PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
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IBAT |
Supply current, VBAT |
All outputs off, |
VBAT = 12 V |
300 |
500 |
700 |
μA |
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ICC |
Supply current, VCC |
All outputs off, |
VBAT = 5.5 V |
1 |
2.6 |
4.2 |
mA |
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V(turnon) |
Turn-on voltage, logic operational, VCC |
VBAT = 5.5 V, |
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2.6 |
3.5 |
4.4 |
V |
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V(ovsd) |
Over-battery-voltage shutdown |
Gate disabled, |
See Figure 16 |
32 |
34 |
36 |
V |
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Vhys(ov) |
Over-battery-voltage reset hysteresis |
0.5 |
1 |
1.5 |
V |
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V(uvsd) |
Under-battery-voltage shutdown, |
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4.1 |
4.8 |
5.4 |
V |
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See Figure 17 |
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Vhys(uv) |
Under-battery-voltage reset hysteresis, |
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200 |
300 |
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VG |
Gate drive voltage |
8 V < VBAT < 24, |
IO = 100 μA |
7 |
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13.5 |
V |
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5.5 V < VBAT < 8 V, |
IO = 100 μA |
5 |
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7 |
V |
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IO(H) |
Maximum current output for drive terminals, |
VOUT = GND |
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0.5 |
1.2 |
2.5 |
mA |
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pullup |
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IO(L) |
Maximum current output for drive terminals, |
VOUT = 7 V |
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0.5 |
1.2 |
2.5 |
mA |
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pulldown |
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V(stb) |
Short-to-battery/shorted-load/open-load |
VCOMPEN = L |
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1.1 |
1.25 |
1.4 |
V |
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detection voltage |
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Vhys(stb) |
Short-to-battery hysteresis |
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100 |
150 |
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VD(open) |
Open-load off-state detection drain voltage |
VCOMPEN = L |
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1.1 |
1.25 |
1.4 |
V |
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threshold |
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Vhys(open) |
Open-load hysteresis |
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40 |
100 |
150 |
mV |
|||
II(open) |
Open-load off-state detection current |
|
|
30 |
60 |
80 |
μA |
|||
II(PU) |
Input pullup current |
|
|
VCC = 5 V, |
VIN = 0 |
|
10 |
|
μA |
|
(CS) |
|
|
|
|||||||
II(PD) |
Input pulldown current |
VCC = 5 V, |
VIN = 5 V |
|
10 |
|
μA |
|||
VI(hys) |
Input voltage hysteresis |
VCC = 5 V |
|
0.6 |
0.85 |
1.1 |
V |
|||
VO(SH) |
High-level serial output voltage |
IO = 1 mA |
|
0.8 VCC |
|
|
V |
|||
VO(SL) |
Low-level serial output voltage |
IO = 1 mA |
|
|
0.1 |
0.4 |
V |
|||
IOZ(SD) |
3-state current serial-data output |
VCC = 0 to 5.5 V |
|
-10 |
1 |
10 |
μA |
|||
VO(CFLT) |
Fault-interrupt output voltage |
IO = 1 mA |
|
|
0.1 |
0.5 |
V |
|||
VI(COMP) |
Fault-external reference voltage |
VCOMPEN = H |
|
1 |
|
3 |
V |
|||
VC |
Output clamp voltage, (TPIC46L01, L02 only) |
dc < 1%, |
tw = 100 μs |
47 |
55 |
63 |
V |
|||
VC |
Output clamp voltage, (TPIC46L03 only) |
dc < 1%, |
tw = 100 μs |
47 |
|
60 |
V |
|||
6 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
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