Texas Instruments TLC2555IDR, TLC2552IDR, TLC2552IDGKR, TLC2552IDGK, TLC2552ID Datasheet

TLC2551, TLC2552, TLC2555 5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 ±MARCH 2000

D

Maximum Throughput . . . 400 KSPS

± TLC2552 ± Dual Channels With

D INL/DNL: ±1 LSB Max, SINAD: 72 dB,

Autosweep

fi = 20 kHz, SFDR: 85 dB, fi = 20 kHz

± TLC2555 ± Single Channel With

D SPI/DSP-Compatible Serial Interfaces With

Pseudo-Differential Input

D Optimized DSP Mode ± Requires FS Only

SCLK up to 20 MHz

D Single 5 V Supply

D Low Power With Autopower Down

± Operating Current : 3.5 mA

D Rail-to-Rail Analog Input With 500 kHz BW

Autopower Down: 8 A

D

Three Options Available:

D Small 8-Pin MSOP and SOIC Packages

± TLC2551 ± Single Channel Input

PACKAGE TOP VIEW

TLC2552

TLC2555

TLC2551

SDO

SDO

SDO

CS

1

8

CS/FS

1

8

CS/FS

1

8

VREF

2

7

FS

VREF

2

7

SCLK

VREF

2

7

SCLK

GND

3

6

VDD

GND

3

6

VDD

GND

3

6

VDD

AIN

4

5

SCLK

AIN0

4

5

AIN1

AIN(+)

4

5

AIN(±)

description

The TLC2551/2552/2555 are a family of high performance, 12-bit, low power, miniature 1.5 s, CMOS analog-to-digital converters (ADC). The TLC255x family uses a 5 V supply. Devices are available with single, dual, or single pseudo-differential inputs. The TLC2551 has a 3-state output chip select (CS), serial output clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a DSP, a frame sync signal (FS) is used to indicate the start of a serial data frame. The TLV2552/55 have a shared CS/FS terminal.

TLC2551/2/5 are designed to operate with very low power consumption. The power saving feature is further enhanced with an autopower-down mode. This product family features a high-speed serial link to modern host processors with SCLK up to 20 MHz. TLC255x family uses the SCLK as the conversion clock, thus providing synchronous operation allowing a minimum conversion time of 1.5 s using 20 MHz SCLK.

AVAILABLE OPTIONS

	PACKAGED DEVICES
TA
	8-MSOP	8-SOIC
	(DGK)	(D)
	TLC2551CDGK
0°C to 70°C
	TLC2552CDGK
	TLC2555CDGK
	TLC2551IDGK	TLC2551ID
± 40°C to 85°C
	TLC2552IDGK	TLC2552ID
	TLC2555IDGK	TLC2555ID

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 ±MARCH 2000

functional block diagram

TLC2551

TLC2552

VDD

REF
	S/H	LOW POWER
AIN		12-BIT
		SAR ADC
	Conversion
		Clock
SCLK	CONTROL
CS
	LOGIC
FS
	GND

VDD

REF
AIN0	Mux
AIN1
SDO
	S/H	LOW POWER	SDO
		SAR ADC
	Conversion
		Clock
SCLK	CONTROL
CS/FS	LOGIC
	GND
TLC2555

VDD

REF
AIN (+)	LOW POWER
S/H	12-BIT	SDO
AIN (±)	SAR ADC
	Conversion
	Clock
SCLK	CONTROL
CS/FS	LOGIC
	GND

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 ±MARCH 2000

Terminal Functions

TLC2551

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AIN

4

I

Analog input channel

1

I

Chip select. A high-to-low transition on the

input removes SDO from 3-state within a maximum setup time.

CS

CS

CS can be used as the FS pin when a dedicated serial port is used. If TLC2551 is attached to a dedicated DSP serial

port, this terminal can be grounded.

FS

7

I

DSP frame sync input. Indication of the start of a serial data frame. Tie this terminal to VDD if not used.

GND

3

I

Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

SCLK

5

I

Output serial clock. This terminal receives the serial SCLK from the host processor.

SDO

8

O

The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state until

falling edge.

CS

The output format is MSB first.

When FS is not used (FS = 1 at the falling edge of

CS): The MSB is presented to the SDO pin after CS falling edge

and output data is valid on the falling edge of SCLK.

When FS is used (FS = 0 at the falling edge of

CS): The MSB is presented to the SDO pin after the falling edge of

FS or the falling edge of

CS

(whichever happens first). Output data is valid on the falling edge of SCLK. (This is

typically used with an active FS from a DSP).

VDD

6

I

Positive supply voltage

VREF

2

I

External reference input

TLC2552/55

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AIN0 /AIN(+)

4

I

Analog input channel 0. (positive input for TLV2555)

AIN1/AIN (±)

5

I

Analog input channel 1 (inverted input for TLV2555)

1

I

Chip select/frame sync. A high-to-low transition on the

CS/FS

CS/FS removes SDO from 3-state within a maximum delay

time.

GND

3

I

Ground return for the internal circuitry. Unless otherwise noted, all voltage measurements are with respect to GND.

SCLK

7

I

Output serial clock. This terminal receives the serial SCLK from the host processor.

SDO

8

O

The 3-state serial output for the A/D conversion result. SDO is kept in the high-impedance state when

CS/FS is

high and presents output data after the CS/FS falling edge until the LSB is presented. The output format is MSB

first. SDO returns to the Hi-Z state after the 16th SCLK. Output data is valid on the falling SCLK edge.

VDD

6

I

Positive supply voltage

VREF

2

I

External reference input

detailed description

The TLC2551/2/5 are successive approximation (SAR) ADCs utilizing a charge redistribution DAC. Figure 1 shows a simplified version of the ADC.

The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is balanced, the conversion is complete and the ADC output code is generated.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 ±MARCH 2000

detailed description (continued)

Charge

Redistribution

DAC

AIN	_	Control
			ADC Code
	+	Logic

GND/AIN(±)

Figure 1. Simplified SAR Circuit

serial interface

OUTPUT DATA FORMAT

MSB	LSB
D15±D4	D3±D0
Conversion result (OD11±OD0)	Don't care

The output data format is binary (unipolar straight binary).

binary

Zero scale code = 000h, Vcode = GND

Full scale code = FFFh, Vcode = VREFP ± 1 LSB

pseudo-differential inputs

The TLC2555 operates in pseudo-differential mode. The inverted input is available on terminal 5. It can have a maximum input ripple of ±0.2 V. This is normally used for ground noise rejection.

control and timing

start of the cycle

TLC2551

DWhen FS is not used ( FS = 1 at the falling edge of CS), the falling edge of CS is the start of the cycle. Output data changes on the rising edge of SCLK. This is typically used for a microcontroller with SPI interface, although it can also be used for a DSP. The microcontroller SPI interface should be programmed for CPOL=0 (serial clock reference to ground) and CPHA=1 (data is valid on the falling edge of serial clock).

DWhen FS is used ( FS is an active signal from a DSP), the falling edge of FS is the start of the cycle. Output data changes on the rising edge of SCLK. This is typically used for a TMS320 DSP. If the TLC2551 is attached to a dedicated DSP serial port. CS terminal can be grounded.

TLC2552/5

The CS and FS inputs are accessed via the same pin (pin 1) on the TLC2552 and TLC2555. The cycle is started by the falling edge transition provided by either a CS (interfacing with a SPI interface microcontroller) signal or FS (interfacing with a TMS320 DSP) signal. Timing for the TLC2555 is much like the TLC2551, with the exception of the CS/FS line.

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555 5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 ±MARCH 2000

detailed description (continued)

TLC2552 channel MUX reset cycle

The TLC2552 uses CS/FS to reset the AIN multiplexer. A short active CS/FS cycle (4±7 SCLKs) resets the MUX to AIN0. If the CS/FS cycle is sufficient to complete the conversion (16 SCLKs plus maximum conversion time), the MUX toggles to the next channel (see Figure 4 for timing).

sampling

The converter sample time is 12 SCLKs beginning on the 5th SCLK received after the converter has received an active CS or FS signal (CS/FS for the TLC2552/5).

conversion

The TLC2551 completes conversion in the following manner. The conversion is started after the 16th SCLK edge. The conversion takes 1.4 s using 20 MHz SCLK plus 0.1 s overhead. Enough time (for conversion) should be allowed before a rising CS/FS edge so that no conversion is terminated prematurely.

TLC2552 input channel selection is toggled on each rising CS /FS edge. The MUX channel can be reset to AIN0 via CS /FS as described in the earlier section and in Figure 5. The input is sampled for 12 SCLKs, converted, and the result is presented on SDO during the next cycle. Care should also be taken to allow enough time between samples to avoid prematurely terminating the conversion, which occurs on a rising CS /FS transition if the conversion is not complete.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TLC2551, TLC2552, TLC2555

5 V, LOW POWER, 12-BIT, 400 KSPS,

SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 ±MARCH 2000

timing diagrams/conversion cycles

DSP Interface

1

2

3

4

5

6

12

13

14

15

16

1

SCLK

CS

FS

t(sample)

t(powerdown)

tc

SDO

OD11

OD10 OD9 OD8 OD7 OD6

OD0

Figure 2. TLC2551 DSP Mode/FS Active

P Interface

1

2

3

4

5

6

7

12

13

14

15

16

1

SCLK

CS

FS

t(sample)

tc

t(powerdown)

SDO

OD11

OD10

OD9

OD8 OD7

OD6

OD5

OD0

Figure 3. TLC2551 Microcontroller Mode/(SPI, CPOL = 0, CPHA = 1)

1

2

3

4

5

1

4

12

16

1

4

12

16

SCLK

<8 SCLKs, MUX

>8 SCLKs, MUX Toggles to AIN1

CS/FS

Resets to AIN0

t(powerdown)

t(sample)

tc

t(sample)

tc

AIN0 Result

SDO

OD11

OD0

Figure 4. TLC2552 Timing

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLC2551, TLC2552, TLC2555 5 V, LOW POWER, 12-BIT, 400 KSPS, SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN

SLAS276 ±MARCH 2000

timing diagrams/conversion cycles (continued)

1

2

3

4

5

6

7

12

13

14

15

16

1

SCLK

CS/FS

t(sample)

t(powerdown)

tc

SDO

OD11

OD10

OD9

OD8

OD7

OD6

OD5

OD0

OD11 OD10

OD9

Figure 5. TLC2555 Timing

use CS as FS input

When interfacing the TLC2551 with the TMS320 DSP, the FSR signal from the DSP may be connected to the CS input if this is the only device on the serial port. This will save one output terminal from the DSP. (Output data changes on the falling edge of SCLK. Default for TLC2552 and TLC2555).

SCLK and conversion speed

It takes 14 conversion clocks to complete the conversion. The conversion clock for the TLC2551/2/5 is equal to SCLK/2. This yields a minimum conversion time of 1.4 µs plus 0.1 µs overhead. These devices can operate with an SCLK up to 20 MHz for the supply voltage range specified. The total conversion time is 14× (1/10M) +16×(1/20M)+ 0.1 µs} = 2.3 µs for a 20 MHz SCLK. This is the minimum cycle time for an active CS or CS/FS signal. If violated, the conversion will terminate, invalidating the next data output cycle.

reference voltage

An external reference is applied via VREF. The voltage level applied to this pin establishes the upper limit of the analog inputs to produce a full-scale reading. The value of VREF and the analog input should not exceed the positive supply or be less than GND, consistent with the specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher than VREF and at zero when the input signal is equal to or lower than GND.

powerdown and powerup initialization

Autopower down is built in to the devices in order to reduce power consumption. The wake-up time is fast enough to provide power down between each cycle. The power-down state is initiated at the end of conversion and wakes up upon a falling edge on CS or FS.

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