Texas Instruments TLC320AD52CPTR, TLC320AD52CPT, TLC320AD52CDWR, TLC320AD52CDW, TLC320AD50CPTR Datasheet

TLC320AD50C/I

TLC320AD52C

Sigma Delta Analog Interface Circuits With

Master Slave Function

Data Manual

2000	Mixed Signal Products

SLAS131D

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (ªCRITICAL APPLICATIONSº). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof.

Copyright 2000, Texas Instruments Incorporated

Contents

Section					Title			Page
1	Introduction . .		. . . . . . . . . . . . .	. . .	. . . . .	. . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . .	1±1
	1.1	Features	. . . . . . . . . . . .	. . .	. . . . .	. . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . .	1±1
	1.2	Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						1±2
	1.3	Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						1±3
	1.4	Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						1±4
	1.5	Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						1±4
	1.6	Definitions and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						1±6
	1.7	Register Functional Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						1±7
2	Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .							2±1
	2.1	Device Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						2±1
		2.1.1	Operating Frequencies and Filter Control . . . . . . . . . . . . . .					2±1
		2.1.2	ADC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±1
		2.1.3	DAC Signal Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±2
		2.1.4	Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±3
		2.1.5	Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±3
		2.1.6	Sigma-Delta ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±5
		2.1.7	Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±5
		2.1.8	Sigma-Delta DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±5
		2.1.9	Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±5
		2.1.10	Analog and Digital Loopback . . . . . . . . . . . . . . . . . . . . . . . . .					2±5
		2.1.11	FIR Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±5
	2.2	Reset and Power-Down Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						2±6
		2.2.1	Software and Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . .					2±6
		2.2.2	Software and Hardware Power Down . . . . . . . . . . . . . . . . . .					2±6
	2.3	Master Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						2±7
	2.4	Data Out (DOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						2±7
		2.4.1	Data Out, Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±7
		2.4.2	Data Out, Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					2±7
	2.5	Data In (DIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .						2±7
	2.6	FC (Hardware Secondary Communication Request) . . . . . . . . . . . . .						2±7
	2.7	Frame-Sync Function for TLC320AD50C . . . . . . . . . . . . . . . . . . . . . . .						2±7
		2.7.1	Frame Sync		Function, Master Mode			2±8
				(FS)
		2.7.2	Frame Sync	(FS)	. . . . . . . . . . . . . . . .Function,Slave Mode			2±8
		2.7.3	Frame-Sync Delayed			(FSD)	. . . . .Function, Master Mode	2±9
		2.7.4	Frame-Sync Delayed			(FSD),	. . . . . . . . . . . . . .Slave Mode	2±9
	2.8	Frame-Sync Function for TLC320AD52C . . . . . . . . . . . . . . . . . . . . . . .						2±11
	2.9	Multiplexed Analog Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . .						2±11

iii

2.9.1 Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2±12

3 Serial Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .			3±1
3.1	Primary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3±1
3.2	Secondary Serial Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3±2
	3.2.1	Hardware Secondary Serial Communication Request . . . .	3±3

3.2.2Software Secondary Serial Communication Request . . . . 3±3

3.3 Conversion Rate Versus Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±4 3.4 Phone Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±4 3.5 DIN and DOUT Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±4

3.5.1Primary Serial Communication DIN and DOUT

Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±4

3.5.2Secondary Serial Communication DIN and DOUT

Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3±5

4 Specifications		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±1
4.1	Absolute Maximum Ratings Over Operating Free-Air
	Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		4±1
4.2	Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .		4±1
	4.2.1	Recommended Operating Conditions, DVDD = 5 V . . . . . .	4±1
	4.2.2	Recommended Operating Conditions, DVDD = 3 V . . . . . .	4±1

4.3Electrical Characteristics Over Recommended Operating

Free-Air Temperature Range, DVDD = 5 V, RL = 600 Ω . . . . . . . . . . . 4±2

4.3.1Digital Inputs and Outputs, MCLK = 8.192 MHz,

fs = 8 kHz, DVDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±2

4.3.2Digital Inputs and Outputs, MCLK = 8.192 MHz,

	fs = 8 kHz, DVDD = 3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	4±2
4.3.3	ADC Channel, MCLK = 8.192 MHz, fs = 8 kHz . . . . . . . . . .	4±2

4.3.4ADC Dynamic Performance, MCLK = 8.192 MHz,

fs = 8 kHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±2 4.3.5 ADC Channel Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 4±3

4.3.6 DAC Path Filter, MCLK = 8.192 MHz, fs = 8 kHz . . . . . . . . 4±3 4.3.7 DAC Dynamic Performance . . . . . . . . . . . . . . . . . . . . . . . . . . 4±4 4.3.8 DAC Channel Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 4±5

4.3.9 Power Supply, AVDD = DVDD = 5 V, No Load . . . . . . . . . . . 4±5 4.3.10 Power-Supply Rejection, AVDD = DVDD = 5 V . . . . . . . . . . 4±5

4.4 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±5 4.4.1 Master Mode Timing Requirements . . . . . . . . . . . . . . . . . . . 4±5 4.4.2 Slave Mode Timing Requirements . . . . . . . . . . . . . . . . . . . . 4±6 4.4.3 Master Mode Switching Characteristics . . . . . . . . . . . . . . . . 4±6 4.4.4 Slave Mode Switching Characteristics . . . . . . . . . . . . . . . . . 4±6 4.4.5 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±6 4.4.6 Other . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4±6

5 Parameter Measurement Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±1 6 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±1

6.1 Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±1 6.2 Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±2

iv

6.3 Control Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±2 6.4 Control Register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6±2

7 Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±1 Appendix A ± Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A±1

v

List of Illustrations

Figure

Title

Page

2±1 Timing Sequence of ADC Channel (Primary Communication Only) . . .

. . . 2±2

2±2 Timing Sequence of ADC Channel (Primary and Secondary

Communication) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . 2±2

2±3 Timing Sequence of DAC Channel (Primary Communication Only) . . .

. . . 2±3

2±4 Timing Sequence of DAC Channel (Primary and Secondary

Communication) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±3

2±5 Register 1 Read Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±4

2±6 Register 1 Write Operation Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±5

2±7 Internal Power-Down Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±6

2±8 Master Device Frame-Sync Signal With Primary and Secondary

Communications (No Slaves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±8

2±9 Master Device Frame-Sync Signal With Primary and Secondary

Communications (With 1 Slave Device) . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±8

2±10 Master Device

and

Output When

Register (D0±D5,

FS

FSD

FSD

Control 3 Register) is 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±9

2±11 Master Device

and

Output After Control 3 Register Is

FS

FSD

Programmed (One Slave Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±9

2±12 Master With Slaves (To DSP Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±10

2±13 Master-Slave Frame-Sync Timing After A Delay Has Been

Programmed Into The FSD Register (D0±D5 of Control 3 Register)

. . . 2±10

2±14 Master Device

and

Output After Control 3 Register

FS

FSD

Is Programmed With 49H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±11

2±15 RC Antialias Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 2±11

2±16 INP and INM Internal Self-Biased (2.5 V) Circuit . . . . . . . . . . . . . . . . . . .

. . 2±12

2±17 Differential Output Drive (Ground Referenced) . . . . . . . . . . . . . . . . . . . . .

. . 2±12

2±18 Digital Input Code vs Analog Output Voltage . . . . . . . . . . . . . . . . . . . . . .

. . 2±12

3±1 Primary Serial Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 3±1

3±2 Hardware and Software Methods to Make a Secondary Request . . . . . .

. . . 3±2

3±3

Output When Hardware Secondary Serial Communication Is Requested

FS

Only Once (No Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 3±3

3±4

Output When Hardware Secondary Serial Communication Is Requested

FS

Only Once (Three Slaves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 3±3

3±5

Output During Software Secondary Serial Communication Request

FS

(No Slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 3±3

3±6 Phone Mode Timing When Phone Mode Is Enabled . . . . . . . . . . . . . . . . .

. . 3±4

vi

3±7 Primary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . . . 3±4 3±8 Secondary Communication DIN and DOUT Data Format . . . . . . . . . . . . . . . 3±5 5±1 Master FS and FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±1 5±2 Slave FS to FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±1 5±3 Master/Slave SCLK to FSD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5±1 5±4 Serial Communication Timing (Master Mode) . . . . . . . . . . . . . . . . . . . . . . . . . 5±2 5±5 Serial Communication Timing (Slave Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 5±2 5±6 ADC Channel Filter Response (MCLK = 8.192 MHz, fs = 8 kHz) . . . . . . . . 5±3 5±7 ADC Channel Filter Passband Ripple (MCLK = 8.192 MHz, fs = 8 kHz) . . 5±3 5±8 DAC Channel Filter Response (MCLK = 8.192 MHz, fs = 8 kHz) . . . . . . . . 5±4 5±9 DAC Channel Filter Passband Ripple (MCLK = 8.192 MHz, fs = 8 kHz) . . 5±4 7±1 Master Device and Slave Device Connections (to DSP Interface) . . . . . . . 7±1 7±2 Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7±2

List of Tables

Table	Title	Page
3±1 Least Significant Bit Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .		3±2
6±1 Register Map . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±1
6±2 Control Register 1 . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±1
6±3 Control Register 2 . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±2
6±4 Control Register 3 . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±2
6±5 Control Register 4 . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	6±2

vii

viii

1 Introduction

The TLC320AD50C, TLC320AD50I, and TLC320AD52C provide high-resolution signal conversion from digital-to-analog (D/A) and from analog-to-digital (A/D) using oversampling sigma-delta technology. This device consists of a pair of 16-bit synchronous serial conversion paths (one for each direction) and includes an interpolation filter before the DAC and a decimation filter after the ADC. Other overhead functions on the chip include timing (sample rate, FSD delay) and control (programmable gain amplifier, PLL, communication protocol, etc.). The sigma-delta architecture produces high resolution A/D and D/A conversion at a low system cost.

Programmable functions of this device can be selected through the serial interface. Options include reset, power down, communications protocol, signal sampling rate, gain control, and system test modes (see section 6). The TLC320AD50C and TLC320AD52C are characterized for operation from 0°C to 70°C, and the TLC320AD50I is characterized for operation from ±40°C to 85°C.

1.1Features

•General-purpose analog interface circuit for V.34+ modem and business audio applications

•16-bit oversampling sigma-delta ADC and DAC

•Serial port interface

•Typical 89-dB SNR (signal-to-noise ratio) for ADC and DAC

•Typical 90-dB THD (signal to total harmonic distortion) for ADC and DAC

•Typical 88-dB dynamic range

•Test mode that includes a digital loopback test and analog loopback test

•Programmable A/D and D/A conversion rate

•Programmable input and output gain control

•Maximum conversion rate: 22.05 kHz

•Single 5-V power supply voltage or 5-V analog and 3-V digital power supply voltage

•Power dissipation (PD) of 120 mW rms typical in the operating mode

•Hardware power-down mode to 7.5 mW

•Internal reference voltage (Vref)

•Differential architecture throughout device

•TLC320AD50C/I can support up to three slave devices; TLC320AD52C can support one slave

•2s complement data format

•ALTDATA terminal provides data monitoring

•Monitor amplifier to monitor input signals

•On-chip phase locked loop (PLL)

1±1

1.2 Functional Block Diagram

INP	5					27	MONOUT
	6
INM		MUX
						PGA
			Sigma	Decimation	Buffer	11
			-Delta				DOUT
				Filter
			ADC
		PGA
	3
AUXP		MUX
AUXM	4					Digital
						Loopback
	Analog					1	REFP
			Vref			2
	Loopback						REFM
OUTP	23	Low	Sigma			12	DIN
				Interpolation
		Pass	-Delta			22
				Filter			M / S
	24	Filter	DAC
OUTM						21
							FSD
		PGA			Buffer	14
							ALTDATA
						17
	16						FC
						20
							FS
PWRDWN						19
	15						SCLK
RESET						13
	28						FLAG
	FILT			Internal
			Clock Circuit		I/O
					Control

MCLK	18	N	PLL (x4)

10

9

7

8

26

25

DVSS DVDD AVDD(PLL) AVSS(PLL) AVSS AVDD

NOTE: Pin numbers shown are for the DW package.

1±2

1.3 Terminal Assignments

DW PACKAGE (TOP VIEW)

						REFP						1			28						FILT
						REFM						2			27						MONOUT
						AUXP						3			26						AVSS
												4			25
						AUXM															AVDD
												5			24
								INP													OUTM
								INM				6			23						OUTP
			AVDD(PLL)									7			22
																					M/S
												8			21
			AVSS(PLL)																		FSD
												9			20
						DVDD															FS
												10			19
						DVSS															SCLK
												11			18
						DOUT															MCLK
								DIN				12			17						FC
						FLAG						13			16
																					PWRDWN
				ALTDATA								14			15
																					RESET
											PT PACKAGE
				AUXM		AUXP REFM				REFP		(TOP VIEW)									MONOUT AV
												NC FILT				NC		NC										NC			AV
																									SS						DD
		48 47 46								45 44 43 42 41 40 39 38 37																											OUTM
																															36
INP		1
																															35						OUTP
INM		2
																															34						NC
NC		3
																															33						NC
NC		4
																															32						NC
AVDD(PLL)		5
																															31						NC
NC		6
																															30						NC
AVSS(PLL)		7
NC		8																													29						M/S
																															28
NC		9																																			FSD
																															27
NC		10																																			FS
		11																													26						SCLK
DVDD
		12																													25						MCLK
DVSS
			13			14 15 16 17 18 19 20 21 22 23 24
				NC		DOUT DIN				FLAG		ALTDATA NC				NC		NC			RESET			PWRDWN				FC			NC

NC ± No internal connection

1±3

1.4 Ordering Information
		PACKAGE
	TA	SMALL OUTLINE	QUAD FLAT PACK
		PLASTIC DIP
			(PT)
		(DW)
	0°C to 70°C	TLC320AD50CDW	TLC320AD50CPT
		TLC320AD52CDW	TLC320AD52CPT
	±40°C to 85°C	TLC320AD50IDW

1.5 Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

NO.

PT

DW

ALTDATA

17

14

I

Alternate data. ALTDATA signals are routed to DOUT during secondary communication if the phone mode

is enabled using control 2 register.

AUXM

48

4

I

Inverting input to auxiliary analog input. AUXM requires an external single-pole antialias filter with a low output

impedance and should be tied to AVSS if not used.

AUXP

47

3

I

Noninverting input to auxiliary analog input. AUXP requires an external single-pole antialias filter with a low

output impedance and should be tied to AVSS if not used.

AVDD

37

25

I

Analog ADC power supply (5 V only) (see Note 1)

AVDD(PLL)

5

7

I

Analog power supply for the internal PLL (5 V only) (see Note 1)

AVSS

39

26

I

Analog ground (see Note 1)

AVSS(PLL)

7

8

I

Analog ground for the internal PLL (see Note 1)

DIN

15

12

I

Data input. DIN receives the DAC input data and register data from the external DSP (digital signal processor)

and is synchronized to SCLK and FS. Data is latched at the falling edge of SCLK when FS is low. DIN is at

high impedance when FS is not active.

DOUT

14

11

O

Data output. DOUT transmits the ADC output bits and register data, and is synchronized to SCLK. Data is

sent out at the rising edge of SCLK when FS is low. DOUT is at high impedance when FS is not activated.

When configured as a master, DOUT is active only during the appropriate time slot. DOUT is in high

impedance during the frame syncs for the slaves.

DVDD

11

9

I

Digital power supply (5 V or 3 V) (see Note 1)

DVSS

12

10

I

Digital ground (see Note 1)

FC

23

17

I

Hardware secondary communication request. When FC is set to high, a secondary communication, followed

by the primary communication, will occur to transfer data between this device and the external controller. FC

is sampled and latched on the rising edge of FS at the end of the primary serial communication. See section

3 for details.

FILT

43

28

O

Bandgap filter. FILT is provided for decoupling of the bandgap reference, and provides 3.2 V. The optimal

capacitor value is 0.1 F (ceramic). This voltage node should be loaded only with a high-impedance dc load.

FLAG

16

13

O

Output flag. During phone mode, FLAG contains the value set in control 2 register.

27

20

I/O

Frame sync.

FS

FS

is an output when the device is configured as a master (M/S

pin tied high). FS is an input when

the device is configured as a slave (M/S pin tied low). When configured as a slave, data will transfer when

FS goes low. FS is internally generated in the master mode for the master device and all slave devices. In

the master mode FS is low during data transfer.

28

21

O

Frame sync delayed output. The

(active-low) output synchronizes a slave device to the frame sync of

FSD

FSD

the master device. FSD is applied to the slave FS input and is the same duration as the master FS signal but

is delayed in time by the number of shift clocks programmed in the control 3 register.

INM

2

6

I

Inverting input to analog modulator. INM requires an external single-pole antialias filter with a low output

impedance.

INP

1

5

I

Noninverting input to analog modulator. INP requires an external single-pole antialias filter with a low output

impedance.

NOTES: 1. Separate analog and digital power and ground pins are supplied on this device. For best operation and results, the PC board designer should utilize separate analog and digital power supplies as well as separate analog and digital ground planes.

2. All digital inputs and outputs are TTL compatible, unless otherwise noted (for DVDD = 5 V).

1±4

1.5 Terminal Functions (Continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

NO.

PT

DW

29

22

I

M/S

Master/slave select input. When M/S is high, the device is the master. When M/S is low, the device is a slave.

MCLK

25

18

I

Master clock. MCLK derives the internal clocks of the sigma±delta analog interface circuit.

MONOUT

40

27

O

Monitor output. MONOUT allows for monitoring of the analog input and is a high-impedance output. The gain

or mute is selected using control 1 register.

OUTM

36

24

O

Inverting output of the DAC. The OUTM output can be loaded with 600 Ω. OUTM is functionally identical with

and complementary to OUTP. OUTM can also be used alone for single-ended operation.

OUTP

35

23

O

Noninverting output of the DAC. The OUTP output can be loaded with 600 Ω. OUTP can also be used alone

for single-ended operation.

22

16

I

Power down. When

is pulled low, the device goes into a power-down mode, the serial interface

PWRDWN

PWRDWN

is disabled. However, all the register values are sustained and the device resumes full power operation without

reinitialization when PWRDWN is pulled high again. PWRDWN resets the counters only and preserves the

programmed register contents (see paragraph 2.2.2 for more information).

REFM

46

2

O

Voltage reference filter output. REFM is provided for low-pass filtering of the internal bandgap reference. The

optimal ceramic capacitor value is 0.1 µF and should be connected between REFM and REFP. DC voltage

at REFM is 0 V.

REFP

45

1

O

Voltage reference filter positive output. REFP is provided for low-pass filtering of the internal bandgap

reference. The optimal ceramic capacitor value is 0.1 µF and should be connected between REFP and REFM.

DC voltage at REFP is 3.2 V.

21

15

I

Reset.

initializes all of the internal registers to their default values. The serial port can be configured

RESET

RESET

to the default state accordingly. See section 6 and paragraph 2.2.1 for more information.

SCLK

26

19

I/O

Shift clock. The SCLK signal clocks serial data in through DIN and out through DOUT during the frame-sync

interval. When configured as an output (M/S high), SCLK is generated internally by multiplying the frame-sync

signal frequency by 256. When configured as an input (M/S low), SCLK is generated externally and must be

synchronous with the master clock and frame sync.

NOTES: 1. Separate analog and digital power and ground pins are supplied on this device. For best operation and results, the PC board designer should utilize separate analog and digital power supplies as well as separate analog and digital ground planes.

2. All digital inputs and outputs are TTL compatible, unless otherwise noted (for DVDD = 5 V).

1±5

1.6 Definitions and Terminology

ADC Channel	The ADC channel refers to all signal processing circuits between the analog input and the digital
	conversion results at DOUT.
Channel Delay	The delay for the analog signal at the ADC input to appear on the digital output. The delay for
	the digital value at the DAC input to appear on the analog output.
d	The alpha character d represents valid programmed or default data in the control register format
	(see Section 3.2) when discussing other data bit portions of the register.
Dxx	Dxx is the bit position in the primary data word (xx is the bit number).
DSxx	DSxx is the bit position in the secondary data word (xx is the bit number).
DAC Channel	DAC channel refers to all signal processing circuits between the digital data word applied to DIN
	and the differential output analog signal available at OUTP and OUTM.
Data Transfer	The time during which data is transferred from DOUT and to DIN. The interval is 16 shift clocks
Interval	and the data transfer is initiated by the falling edge of the frame-sync signal.
FIR	Finite duration impulse response
fs	The sampling frequency
Frame Sync and	Frame sync and sampling period is the time between falling edges of successive primary
Sampling Period	frame-sync signals. It is always equal to 256 SCLK.
Frame Sync	Frame sync refers only to the falling edge of the signal that initiates the data transfer interval.
	The primary frame sync starts the primary communications, and the secondary frame sync
	starts the secondary communications.
Frame-Sync	The frame-sync interval is the time period occupied by 16 shift clocks. The frame-sync signal
Interval	goes high on the seventeenth rising edge of SCLK.
Host	A host is any processing system that interfaces to DIN, DOUT, SCLK,		and/or MCLK.
		FS,
PGA	Programmable gain amplifier
Primary	Primary communications refers to the digital data transfer interval. Since the device is
Communications	synchronous, the signal data words from the ADC channel and to the DAC channel occur
	simultaneously.
Secondary	Secondary communications refers to the digital control and configuration data transfer interval
Communications	into DIN and the register read data cycle from DOUT. The data transfer interval occurs when
	requested by hardware or software.
Signal Data	This refers to the input signal and all of the converted representations through the ADC channel
	and the signal through the DAC channel to the analog output. This is contrasted with the purely
	digital software control data.
X	The alpha character X represents a don't care bit-position within the control register format.

1±6

1.7 Register Functional Summary

There are seven control registers that are used as follows:

Register 0 The No-Op register. Addressing register 0 allows secondary communications requests without altering any other register.

Register 1 Control register 1. The data in this register controls:

•Software reset

•Software power down

•Normal or auxiliary analog inputs enabling

•Normal or auxiliary analog inputs monitoring

•Selection of monitor amplifier output gain

•Selection of digital loopback

•Selection of16-bit or (15+1)-bit mode of DAC operation

Register 2 Control register 2. The data in this register:

•Contains the output value of FLAG

•Selects phone mode

•Contains the output flag indicating a decimator FIR filter overflow

•Selects either 16-bit mode or (15+1)-bit mode of ADC operation

•Enables analog loopback

Register 3 Control register 3. The data in this register:

•Sets the number of SCLK delays between FS and FSD

•Informs the master device of how many slaves are connected in the chain

Register 4 Control register 4. The data in this register:

•Selects the amplifier gain for the input and output amplifiers

•Sets the sample rate by choosing the value of N from 1 to 8 where fs = MCLK/(128 N) or MCLK/(512 N)

•Selects the PLL. If the PLL is selected, the sampling rate is set to MCLK/(128 N). If the PLL is bypassed, the sampling rate can be set to MCLK/(512 N).

Register 5 Reserved for factory test. Do not write to this register.

Register 6 Reserved for factory test. Do not write to this register.

1±7

1±8