Texas Instruments TLC2543MJB, TLC2543MJ, TLC2543IN, TLC2543IFNR, TLC2543IFN Datasheet

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079D ± DECEMBER 1993 ± REVISED MAY 1997

D

12-Bit-Resolution A/D Converter

DB, DW, J, OR N PACKAGE

D 10-μs Conversion Time Over Operating

(TOP VIEW)

Temperature

AIN0

VCC

1

20

D 11 Analog Input Channels

AIN1

2

19

EOC

D 3 Built-In Self-Test Modes

AIN2

3

18

I/O CLOCK

Inherent Sample-and-Hold Function

D

AIN3

4

17

DATA INPUT

D Linearity Error . . . ± 1 LSB Max

AIN4

5

16

DATA OUT

AIN5

D On-Chip System Clock

6

15

CS

AIN6

7

14

REF+

D End-of-Conversion Output

AIN7

8

13

REF±

D Unipolar or Bipolar Output Operation

AIN8

9

12

AIN10

(Signed Binary With Respect to 1/2 the

GND

10

11

AIN9

Applied Voltage Reference)

D Programmable MSB or LSB First

FK OR FN PACKAGE

D

Programmable Power Down

(TOP VIEW)

D Programmable Output Data Length

AIN2

AIN1

AIN0

CC

D

CMOS Technology

D Application Report Available²

V EOC

AIN3

3

2

1

20 19

I/O CLOCK

description

4

18

AIN4

5

17

DATA INPUT

The TLC2543C and TLC2543I are 12-bit, switched-

AIN5

6

16

DATA OUT

capacitor, successive-approximation, analog-to-

AIN6

7

15

CS

digital converters. Each device has three control

AIN7

8

14

REF+

9

10 11 12 13

inputs [chip select (CS), the input-output clock (I/O

CLOCK), and the address input (DATA INPUT)] and

AIN8

GND

AIN9

AIN10 REF±

is designed for communication with the serial port of

a host processor or peripheral through a serial 3-state output. The device allows high-speed data transfers from the host.

In addition to the high-speed converter and versatile control capability, the device has an on-chip 14-channel multiplexer that can select any one of 11 inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic. At the end of conversion, the end-of-conversion (EOC) output goes high to indicate that conversion is complete. The converter incorporated in the device features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error conversion over the full operating temperature range.

The TLC2543C is characterized for operation from TA = 0°C to 70°C. The TLC2543I is characterized for operation from TA = ±40°C to 85°C. The TLC2543M is characterized for operation from TA = ±55°C to 125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

² Microcontroller Based Data Acquisition Using the TLC2543 12-bit Serial-Out ADC (SLAA012)

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1997, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079D ± DECEMBER 1993 ± REVISED MAY 1997

AVAILABLE OPTIONS

			PACKAGE
TA	SMALL OUTLINE		PLASTIC CHIP		PLASTIC CHIP	PLASTIC DIP	PLASTIC DIP
			CARRIER		CARRIER
	(DB)²	(DW)²	(FK)		(FN)²	(J)	(N)
0°C to 70°C	TLC2543CDB	TLC2543CDW	Ð		TLC2543CFN	Ð	TLC2543CN
± 40°C to 85°C	Ð	TLC2543IDW	Ð		TLC2543IFN	Ð	TLC2543IN
± 55°C to 125°C	Ð	Ð	TLC2543MFK		Ð	TLC2543MJ	Ð

² Available in tape and reel and ordered as the TLC2543CDBLE, TLC2543CDWR, TLC2543IDWR, TLC2543CFNR, or TLC2543IFNR.

functional block diagram
				REF +	REF ±
				14	13
AIN0	1		Sample-and-	12-Bit
				Analog-to-Digital
AIN1	2		Hold
				Converter
AIN2	3		Function	(Switched Capacitors)
AIN3	4
AIN4	5	14-Channel
AIN5	6			12
AIN6	7	Analog
		Multiplexer
AIN7	8
				Output	12	12-to-1 Data
AIN8	9						16	DATA
				Data		Selector and
AIN9	11							OUT
		4		Register		Driver
	12		Input Address
AIN10
			Register
						4
	3
		Self-Test		Control Logic
				and I/O
		Reference		Counters
DATA	17						19	EOC
INPUT
I/O CLOCK	18
	15
CS

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079D ± DECEMBER 1993 ± REVISED MAY 1997

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

NO.

AIN0 ± AIN10

1 ± 9,

I

Analog input. These 11 analog-signal inputs are internally multiplexed. The driving source impedance should

11, 12

be less than or equal to 50 Ω for 4.1-MHz I/O CLOCK operation and be capable of slewing the analog input

voltage into a capacitance of 60 pF.

15

I

Chip select. A high-to-low transition on

resets the internal counters and controls and enables DATA OUT,

CS

CS

DATA INPUT, and I/O CLOCK. A low-to-high transition disables DATA INPUT and I/O CLOCK within a setup

time.

DATA INPUT

17

I

Serial-data input. A 4-bit serial address selects the desired analog input or test voltage to be converted next.

The serial data is presented with the MSB first and is shifted in on the first four rising edges of I/O CLOCK.

After the four address bits are read into the address register, I/O CLOCK clocks the remaining bits in order.

DATA OUT

16

O

The 3-state serial output for the A/D conversion result. DATA OUT is in the high-impedance state when

CS

is high and active when

CS

is low. With a valid CS, DATA OUT is removed from the high-impedance state

and is driven to the logic level corresponding to the MSB/LSB² value of the previous conversion result. The

next falling edge of I/O CLOCK drives DATA OUT to the logic level corresponding to the next MSB / LSB, and

the remaining bits are shifted out in order.

EOC

19

O

End of conversion. EOC goes from a high to a low logic level after the falling edge of the last I/O CLOCK and

remains low until the conversion is complete and the data is ready for transfer.

GND

10

Ground. GND is the ground return terminal for the internal circuitry. Unless otherwise noted, all voltage

measurements are with respect to GND.

I/O CLOCK

18

I

Input/output clock. I/O CLOCK receives the serial input and performs the following four functions:

1. It clocks the eight input data bits into the input data register on the first eight rising edges of I/O CLOCK

with the multiplexer address available after the fourth rising edge.

2. On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplexer input

begins charging the capacitor array and continues to do so until the last falling edge of the I/O

CLOCK.

3. It shifts the 11 remaining bits of the previous conversion data out on DATA OUT. Data changes on

the falling edge of I/O CLOCK.

4. It transfers control of the conversion to the internal state controller on the falling edge of the last

I/O CLOCK.

REF +

14

I

Positive reference voltage The upper reference voltage value (nominally VCC) is applied to REF+. The

maximum input voltage range is determined by the difference between the voltage applied to this terminal and

the voltage applied to the REF ± terminal.

REF ±

13

I

Negative reference voltage. The lower reference voltage value (nominally ground) is applied to REF ±.

VCC

20

Positive supply voltage

² MSB/LSB = Most significant bit /least significant bit

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079D ± DECEMBER 1993 ± REVISED MAY 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±0.5 V to 6.5	V
Input voltage range, VI (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to VCC + 0.3	V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±0.3 V to VCC + 0.3	V
Positive reference voltage, Vref + . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . VCC + 0.1	V
Negative reference voltage, Vref ± . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . ±0.1 V
Peak input current, II (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . ± 20 mA
Peak total input current, II (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . ± 30 mA
Operating free-air temperature range, TA: TLC2543C . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . 0°C to 70°C
TLC2543I . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±40°C to 85°C
TLC2543M . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . ±55°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds . . . . . . . . . . . . . . .	. . . . . . . . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to the GND terminal with REF ± and GND wired together (unless otherwise noted).

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, VCC

4.5

5

5.5

V

Positive reference voltage, Vref + (see Note 2)

VCC

V

Negative reference voltage, Vref ± (see Note 2)

0

V

Differential reference voltage, Vref + ± Vref ± (see Note 2)

2.5

VCC

VCC + 0.1

V

Analog input voltage (see Note 2)

0

VCC

V

High-level control input voltage, VIH

VCC = 4.5 V to 5.5 V

2

V

Low-level control input voltage, VIL

VCC = 4.5 V to 5.5 V

0.8

V

Clock frequency at I/O CLOCK

0

4.1

MHz

Setup time, address bits at DATA INPUT before I/O CLOCK↑, tsu(A) (see Figure 4)

100

ns

Hold time, address bits after I/O CLOCK↑, th(A) (see Figure 4)

0

ns

Hold time,

low after last I/O CLOCK↓, th(CS) (see Figure 5)

0

ns

CS

Setup time,

low before clocking in first address bit, tsu(CS) (see Note 3 and Figure 5)

1.425

ms

CS

Pulse duration, I/O CLOCK high, twH(I/O)

120

ns

Pulse duration, I/O CLOCK low, twL(I/O)

120

ns

Transition time, I/O CLOCK high to low, tt(I/O) (see Note 4 and Figure 6)

1

ms

Transition time, DATA INPUT and

tt(CS)

10

ms

CS,

TLC2543C

0

70

Operating free-air temperature, TA

°C

TLC2543I

± 40

85

TLC2543M

± 55

125

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that applied to REF± convert as all zeros (000000000000).

3.To minimize errors caused by noise at the CS input, the internal circuitry waits for a setup time after CS↓before responding to control input signals. No attempt should be made to clock in an address until the minimum CS setup time has elapsed.

4.This is the time required for the clock input signal to fall from VIHmin to VILmax or to rise from VILmax to VIHmin. In the vicinity of normal room temperature, the devices function with input clock transition time as slow as 1 ms for remote data acquisition applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079D ± DECEMBER 1993 ± REVISED MAY 1997

electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TLC2543C, TLC2543I

UNIT

MIN

TYP²

MAX

VOH

High-level output voltage

VCC = 4.5 V,

IOH = ±1.6 mA

2.4

V

VCC = 4.5 V to 5.5 V,

IOH = ±20 μA

VCC ± 0.1

VOL

Low-level output voltage

VCC = 4.5 V,

IOL = 1.6 mA

0.4

V

VCC = 4.5 V to 5.5 V,

IOL = 20 μA

0.1

VO = VCC,

1

2.5

IOZ

High-impedance off-state output

CS

at VCC

μA

current

VO = 0,

CS at VCC

1

± 2.5

IIH

High-level input current

VI = VCC

1

2.5

μA

IIL

Low-level input current

VI = 0

1

± 2.5

μA

ICC

Operating supply current

at 0 V

1

2.5

mA

CS

ICC(PD)

Power-down current

For all digital inputs,

4

25

μA

0 ≤ VI ≤ 0.5 V or VI ≥ VCC ± 0.5 V

Selected channel leakage

Selected channel at VCC,

Unselected channel at 0 V

1

Selected channel at 0 V,

μA

current

± 1

Unselected channel at VCC

Maximum static analog

Vref + = VCC,

Vref ± = GND

1

2.5

μA

reference current into REF +

Ci

Input

Analog inputs

30

60

pF

capacitance

Control inputs

5

15

² All typical values are at VCC = 5 V, TA = 25°C.

electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz (unless otherwise noted)

PARAMETER

TEST CONDITIONS

TLC2543M

UNIT

MIN

TYP²

MAX

VOH

High-level output voltage

VCC = 4.5 V,

IOH = ±1.6 mA

2.4

V

VCC = 4.5 V to 5.5 V,

IOH = ±20 μA

VCC ± 0.1

VOL

Low-level output voltage

VCC = 4.5 V,

IOL = 1.6 mA

0.4

V

VCC = 4.5 V to 5.5 V,

IOL = 20 μA

0.1

VO = VCC,

1

2.5

IOZ

High-impedance off-state output

CS

at VCC

μA

current

VO = 0,

CS at VCC

1

± 2.5

IIH

High-level input current

VI = VCC

1

10

μA

IIL

Low-level input current

VI = 0

1

± 10

μA

ICC

Operating supply current

at 0 V

1

10

mA

CS

ICC(PD)

Power-down current

For all digital inputs,

4

25

μA

0 ≤ VI ≤ 0.5 V or VI ≥ VCC ± 0.5 V

Selected channel leakage

Selected channel at VCC,

Unselected channel at 0 V

10

Selected channel at 0 V,

μA

current

± 10

Unselected channel at VCC

Maximum static analog

Vref + = VCC,

Vref ± = GND

1

2.5

μA

reference current into REF +

Ci

Input

Analog inputs

30

60

pF

capacitance

Control inputs

5

15

² All typical values are at VCC = 5 V, TA = 25°C.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079D ± DECEMBER 1993 ± REVISED MAY 1997

operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 4.5 V to 5.5 V, f(I/O CLOCK) = 4.1 MHz

PARAMETER

TEST CONDITIONS

MIN TYP²

MAX

UNIT

EL

Linearity error (see Note 5)

See Figure 2

± 1

LSB

ED

Differential linearity error

See Figure 2

± 1

LSB

EO

Offset error (see Note 6)

See Note 2 and

± 1.5

LSB

Figure 2

EG

Gain error (see Note 6)

See Note 2 and

± 1

LSB

Figure 2

ET

Total unadjusted error (see Note 7)

± 1.75

LSB

DATA INPUT = 1011

2048

Self-test output code (see Table 3 and Note 8)

DATA INPUT = 1100

0

DATA INPUT = 1101

4095

tconv

Conversion time

See Figures 9 ± 14

8

10

ms

10 + total

tc

Total cycle time (access, sample, and conversion)

See Figures 9 ± 14

I/O CLOCK

ms

and Note 9

periods +

td(I/O-EOC)

See Figures 9 ± 14

I/O

tacq

Channel acquisition time (sample)

4

12

CLOCK

and Note 9

periods

tv

Valid time, DATA OUT remains valid after I/O CLOCK↓

See Figure 6

10

ns

td(I/O-DATA)

Delay time, I/O CLOCK↓ to DATA OUT valid

See Figure 6

150

ns

td(I/O-EOC)

Delay time, last I/O CLOCK↓ to EOC↓

See Figure 7

1.5

2.2

ms

td(EOC-DATA)

Delay time, EOC↑ to DATA OUT (MSB / LSB)

See Figure 8

100

ns

tPZH, tPZL

Enable time,

↓ to DATA OUT (MSB / LSB driven)

See Figure 3

0.7

1.3

ms

CS

tPHZ, tPLZ

Disable time,

↑ to DATA OUT (high impedance)

See Figure 3

70

150

ns

CS

tr(EOC)

Rise time, EOC

See Figure 8

15

50

ns

tf(EOC)

Fall time, EOC

See Figure 7

15

50

ns

tr(bus)

Rise time, data bus

See Figure 6

15

50

ns

tf(bus)

Fall time, data bus

See Figure 6

15

50

ns

Delay time, last I/O CLOCK↓ to

↓ to abort conversion

td(I/O-CS)

CS

5

ms

(see Note 10)

² All typical values are at TA = 25°C.

NOTES: 2. Analog input voltages greater than that applied to REF + convert as all ones (111111111111), while input voltages less than that applied to REF ± convert as all zeros (000000000000).

5.Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

6.Gain error is the difference between the actual midstep value and the nominal midstep value in the transfer diagram at the specified gain point after the offset error has been adjusted to zero. Offset error is the difference between the actual midstep value and the nominal midstep value at the offset point.

7.Total unadjusted error comprises linearity, zero-scale, and full-scale errors.

8.Both the input address and the output codes are expressed in positive logic.

9.I/O CLOCK period = 1 /(I/O CLOCK frequency) (see Figure 7).

10.Any transitions of CS are recognized as valid only when the level is maintained for a setup time. CS must be taken low at ≤ 5 ms of the tenth I/O CLOCK falling edge to ensure a conversion is aborted. Between 5 ms and 10 ms, the result is uncertain as to whether the conversion is aborted or the conversion results are valid.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079D ± DECEMBER 1993 ± REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION

		15 V
		50 Ω
C1	C2	C3
10 μF	0.1 μF	470 pF

	_	TLC2543
		10 Ω
	U1	AIN0 ± AIN10
VI	+

C1

C2

C3

10 μF

0.1 μF

470 pF

50 Ω

± 15 V

LOCATION

DESCRIPTION

PART NUMBER

U1

OP27

Ð

C1

10-μF 35-V tantalum capacitor

Ð

C2

0.1-μF ceramic NPO SMD capacitor

AVX 12105C104KA105 or equivalent

C3

470-pF porcelain Hi-Q SMD capacitor

Johanson 201S420471JG4L or equivalent

Figure 1. Analog Input Buffer to Analog Inputs AIN0±AIN10

Test Point	VCC	Test Point	VCC
	RL = 2.18 kΩ		RL = 2.18 kΩ
EOC		DATA OUT
CL = 50 pF	12 kΩ	CL = 100 pF	12 kΩ

		Figure 2. Load Circuits
				Data
				Valid
CS		2 V	DATA INPUT	2 V
	0.8 V			0.8 V
tPZH, tPZL		tPHZ, tPLZ		th(A)
				tsu(A)
DATA	2.4 V	90%	I/O CLOCK
				0.8 V
OUT	0.4 V	10%
Figure 3. DATA OUT to Hi-Z Voltage Waveforms			Figure 4. DATA INPUT and I/O CLOCK
				Voltage Waveforms

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

7

TLC2543C, TLC2543I, TLC2543M

12-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079D ± DECEMBER 1993 ± REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION

	CS		2 V
		0.8 V
	tsu(CS)		th(CS)
	I/O CLOCK	Last	0.8 V
	0.8 V
		Clock

NOTE A: To ensure full conversion accuracy, it is recommended that no input signal change occurs while a conversion is ongoing.

Figure 5. CS and I/O CLOCK Voltage Waveforms

tt(I/O)			tt(I/O)
I/O CLOCK	2 V		2 V	0.8 V
	0.8 V
			0.8 V
			I/O CLOCK Period
td(I/O-DATA)
	tv
DATA OUT		2.4 V	2.4 V
		0.4 V	0.4 V

tr(bus), tf(bus)

Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms

I/O CLOCK	Last				0.8 V
	Clock
	td(I/O-EOC)
EOC					2.4 V

0.4 V

tf(EOC)

Figure 7. I/O CLOCK and EOC Voltage Waveforms

		tr(EOC)
	EOC	2.4 V
		0.4 V
		td(EOC-DATA)
	DATA OUT	2.4 V
		0.4 V
		Valid MSB

Figure 8. EOC and DATA OUT Voltage Waveforms

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLC2543C, TLC2543I, TLC2543M 12-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS079D ± DECEMBER 1993 ± REVISED MAY 1997

PARAMETER MEASUREMENT INFORMATION

CS

(see Note A)

I/O

1

2

3

4

5

6

7

8

11

12

1

CLOCK

Access Cycle B

Sample Cycle B

DATA

Hi-Z State

A11

A10

A9

A8

A7

A6

A5

A4

A1

A0

B11

OUT

MSB

Previous Conversion Data

LSB

DATA

INPUT

B7

B6

B5

B4

B3

B2

B1

B0

C7

MSB

LSB

EOC

Shift in New Multiplexer Address,

tconv

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Initialize

Interval

Initialize

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 9. Timing for 12-Clock Transfer Using CS With MSB First

CS

(see Note A)

I/O

1

2

3

4

5

6

7

8

11

12

1

CLOCK

Access Cycle B

Sample Cycle B

DATA

A11

A10

A9

A8

A7

A6

A5

A4

A1

A0

Low Level

B11

OUT

MSB

Previous Conversion Data

LSB

DATA

INPUT

B7

B6

B5

B4

B3

B2

B1

B0

C7

MSB

LSB

EOC

Shift in New Multiplexer Address,

tconv

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Initialize

Interval

Initialize

NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS setup time has elapsed.

Figure 10. Timing for 12-Clock Transfer Not Using CS With MSB First

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