Texas Instruments TLC5617ACD, TLC5617IP, TLC5617IDR, TLC5617CP, TLC5617ID Datasheet

TLC5617, TLC5617A

PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS151B – JULY 1997 – REVISED MARCH 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Programmable Settling Time to 0.5 LSB

2.5 µs or 12.5 µs Typ

D

Two 10-Bit CMOS Voltage Output DACs in
an 8 Pin Package

D

Simultaneous Updates for DAC A
and DAC B

D

Single Supply Operation

D

3-Wire Serial Interface

D

High-Impedance Reference Inputs

D

Voltage Output Range ...2 Times the
Reference Input Voltage

D

Software Power Down Mode

D

Internal Power-On Reset

D

TMS320 and SPI Compatible

D

Low Power Consumption:
– 3 mW Typ in Slow Mode
– 8 mW Typ in Fast Mode

D

Input Data Update Rate of 1.21 MHz

D

Monotonic Over Temperature

applications

D

Battery Powered Test Instruments

D

Digital Offset and Gain Adjustment

D

Battery Operated/Remote Industrial
Controls

D

Machine and Motion Control Devices

D

Cellular Telephones

The TLC5617 and TLC5617A are dual 10-bit
voltage output digital-to-analog converters (DAC)
with buffered reference inputs (high impedance).
The DACs have an output voltage range that is
two times the reference voltage, and the DACs are
monotonic. The devices are simple to use,
running from a single supply of 5 V. A power-on
reset function is incorporated to ensure repeat­able start-up conditions.

Digital control of the TLC5617 is over a 3-wire CMOS compatible serial bus. The device receives a 16-bit word
for programming and producing the analog output. The digital inputs feature Schmitt triggers for high noise
immunity. Digital communication protocols include the SPI, QSPI, and Microwire standards.

Two versions of this device are available. The TLC5617 does not have any internal state machine and is
dependent on all external timing signals. The TLC5617A has an internal state machine that will count the
number of clocks from the falling edge of CS

and then updates and disables the device from accepting further
data inputs. The TLC5617A is recommended for TMS320 and SPI processors and the TLC5617 is
recommended only for use in SPI or 3-wire serial port processors. The TLC5617A is backward compatible and
designed to work in TLC5617 designed systems.

The 8-terminal small-outline D package allows digital control of analog functions in space-critical applications.
The TLC5617C is characterized for operation from 0°C to 70°C. The TLC5617I is characterized for operation
from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SPI and QSPI are trademarks of Motorola, Inc.
Microwire is a trademark of National Semiconductor Corporation.

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4

8
7
6
5

DIN

SCLK

CS

OUT A

V

DD

OUT B
REFIN
AGND

D PACKAGE

(TOP VIEW)

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS151B – JULY 1997 – REVISED MARCH 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

†

(D)

0°C to 70°C

TLC5617CD
TLC5617ACD

–40°C to 85°C

TLC5617ID
TLC5617AID

†

Available in tape and reel as the TLC5617CDR
and the TLC5617IDR

DEVICE

COMPATIBILITY

TLC5617 SPI, QSPI, and Microwire
TLC5617A TMS320Cxx, SPI, QSPI, and Microwire

functional block diagram

_

+

DAC

10-Bit DAC Register Latch A

Power-Up

Reset

Control

Logic

16-Bit Shift Register

4

Program

Bits

12 Data Bits

(LSB) (MSB)

REFIN

AGND

CS

SCLK

DIN

OUT A
(Voltage Output)

_
+

RR

DAC A

10-Bit DAC Register Latch B

×2

Double

Buffer
Latch

_
+

_

+

OUT B
(Voltage Output)

DACB

DAC

R

×2

R

4

7

6

5

3
2
1

TLC5617, TLC5617A

PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS151B – JULY 1997 – REVISED MARCH 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

AGND 5 Analog ground
CS 3 I Chip select, active low
DIN 1 I Serial data input
OUT A 4 O DAC A analog output
OUT B 7 O DAC B analog output
REFIN 6 I Reference voltage input
SCLK 2 I Serial clock input
V

DD

8 Positive power supply

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage (VDD to AGND) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range to AGND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage range to AGND – 0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage at OUT from external source V

DD

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current at any terminal ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLC5617C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TLC5617I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

DD

4.5 5 5.5 V

High-level digital input voltage, V

IH

VDD = 5 V 0.7 V

DD

V

Low-level digital input voltage, V

IL

VDD = 5 V 0.3 V

DD

V

Reference voltage, V

ref

to REFIN terminal 1 2.048 VDD–1.1 V

Load resistance, R

L

2 kΩ

p

p

TLC5617C 0 70 °C

Operating free-air temperature, T

A

TLC5617I –40 85 °C

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS151B – JULY 1997 – REVISED MARCH 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%,
V

ref

(REFIN)= 2.048 V (unless otherwise noted)

static DAC specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Resolution 10 bits
Integral nonlinearity (INL), end point adjusted V

ref(REFIN)

= 2.048 V , See Note 1 ±1 LSB

Differential nonlinearity (DNL) V

ref(REFIN)

= 2.048 V , See Note 2 ±0.1 ± 0.5 LSB

E

ZS

Zero-scale error (offset error at zero scale) V

ref(REFIN)

= 2.048 V , See Note 3 ±3 LSB

Zero-scale-error temperature coefficient V

ref(REFIN)

= 2.048 V , See Note 4 3 ppm/°C

E

G

Gain error V

ref(REFIN)

= 2.048 V , See Note 5 ±3 LSB

Gain error temperature coefficient V

ref(REFIN)

= 2.048 V , See Note 6 1 ppm/°C

Zero scale

80

pp

Gain

Slo

w

80

PSRR

Power-su ly rejection ratio

Zero scale

See Notes 7 and 8

80

dB

Gain

Fast

80

NOTES: 1. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output

from the line between zero and full scale excluding the effects of zero code and full-scale errors.

2. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal
1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.

3. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

4. Zero-scale-error temperature coefficient is given by: EZSTC = [EZS(T

max

) – EZS(T

min

)]/V

ref

× 106/(T

max

– T

min

).

5. Gain error is the deviation from the ideal output (V

ref

– 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.

6. Gain temperature coefficient is given by: EGTC = [EG(T

max

) – EG (T

min

)]/V

ref

× 106/(T

max

– T

min

).

7. Zero-scale-error rejection ratio (EZS-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of
this signal imposed on the zero-code output voltage.

8. Gain-error rejection ratio (EG-RR) is measured by varying the VDD from 4.5 V to 5.5 V dc and measuring the proportion of this signal
imposed on the full-scale output voltage after subtracting the zero scale change.

OUT A and OUT B output specifications

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

O

Voltage output RL = 10 kΩ 0 VDD–0.4 V
Output load regulation accuracy V

O(OUT)

= 2V, RL from 10 kΩ to 2 kΩ 0.5 LSB

I

OSC

Output short circuit current V

O(OUT A)

or V

O(OUT B)

to VDD or AGND 20 mA

I

O(sink)

Output sink current V

O(OUT)

> 0.25 V 5 mA

I

O(source)

Output source current V

O(OUT)

< 4.75 V 5 mA

reference input (REFIN)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

I

Input voltage 0 VDD–2 V

R

i

Input resistance 10 MΩ

C

i

Input capacitance 5 pF
Reference feedthrough REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 9) –80 dB

p

Slow 0.5

Reference in ut bandwidth (f–3dB)

REFIN

= 0.2

V

pp

+ 1.024 V dc

Fast 1

MHz

NOTE 9: Reference feedthrough is measured at the DAC output with an input code = 00 hex and a V

ref(REFIN)

input = 1.024 V dc + 1 V

pp

at 1 kHz.

TLC5617, TLC5617A

PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS151B – JULY 1997 – REVISED MARCH 2000

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%,
V

ref

(REFIN)= 2.048 V (unless otherwise noted) (continued)

digital inputs (DIN, SCLK, CS)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

IH

High-level digital input current VI = V

DD

±1 µA

I

IL

Low-level digital input current VI = 0 V ±1 µA

C

i

Input capacitance 8 pF

power supply

PARAMETER TEST CONDITIONS MIN TYP MAX

UNIT

Supply voltage, V

DD

4.5 5 5.5 V

pp

VDD = 5.5 V,

Slow 0.6 1

IDDPower supply current

No load

,

All inputs = 0 V or V

DD

Fast 1.6 2.5

mA

Power down supply current D13 = 0 (see Table 3) 1 µA

operating characteristics over recommended operating free-air temperature range, VDD = 5 V ±5%,
V

ref(REFIN)

= 2.048 V (unless otherwise noted)

analog output dynamic performance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

p

CL = 100 pF,

V

ref(REFIN)

= 2.048 V ,

°

Slow 0.3 0.5

SR

Output slew rate

R

L

= 10 kΩ,

Code 32 to Code 1024,

T

A

=

25°C

,

VO from 10% to 90%

Fast

2.4 3

V/µs

p

To ±0.5 LSB,

CL = 100 pF,

Slow 12.5

tsOutput settling time

,

RL = 10 kΩ,

See Note 10

Fast

2.5

µ

s

Output settling time, code To ±0.5 LSB,

CL = 100 pF,

Slow 2

t

s(c)

g,

to code

,

RL = 10 kΩ,

See Note 11

Fast

2

µ

s

Glitch energy

DIN = All 0s to all 1s,
f

(SCLK)

= 100 kHz

CS = VDD,

5 nV–s

V

ref(REFIN)

= 1 Vpp at 1 kHz and 10 kHz + 1.024 V dc,

Slow 78

S/(N+D)

Signal to noise + distortion

()

Input code = 10 0000 0000

Fast 81

dB

NOTES: 10. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change

of 020 hex to 3FF hex or 3FF hex to 020 hex.

11. Setting time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of one count.

digital input timing requirements

MIN NOM MAX UNIT

t

su(DS)

Setup time, DIN before SCLK low 5 ns

t

h(DH)

Hold time, DIN valid after SCLK low 5 ns

t

su(CSS)

Setup time, CS low to SCLK low 5 ns

t

su(CS1)

Setup time, SCLK ↑ to CS ↑, external end-of-write 10 ns

t

su(CS2)

Setup time, SCLK ↑ to CS ↓, start of next write cycle 5 ns

t

w(CL)

Pulse duration, SCLK low 25 ns

t

w(CH)

Pulse duration, SCLK high 25 ns

TLC5617, TLC5617A
PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS151B – JULY 1997 – REVISED MARCH 2000

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER MEASUREMENT INFORMATION

ООООООО

t

su(CSS)

t

w(CL)

t

w(CH)

CS

SCLK

DIN

t

su(DS)

t

h(DH)

D15 D14 D13 D12 D11 D0

t

s

DAC OUT

A/B

≤ Final Value ±0.5 LSB

(see Note A)

NOTE A: SCLK must go high after the 16th falling clock edge.

ПППППП

Program Bits (4)

DAC Data

Bits (12)

t

su(CS1)

t

su(CS2)

Figure 1. Timing Diagram for the TLC5617A

PARAMETER MEASUREMENT INFORMATION

Figure 2

15

10

0

–5

012

Output Sink Current – mA

20

25

Output Load Voltage – V

OUTPUT SINK CURRENT (FAST MODE)

vs

OUTPUT LOAD VOLTAGE

30

3.5

5

35

40

1.50.5 2.5 3 4

4.5

VCC = 5 V,
Input Code = 0

Figure 3

–30

–20

–10

0

Output Source Current – mA

–40

–50

Output Load Voltage – V

OUTPUT SOURCE CURRENT (FAST MODE)

vs

OUTPUT LOAD VOLTAGE

–60

0 0.5 1

1.5 2

2.5 3 3.5 4 4.5

VDD = 5 V,
Input Code = 4095