Texas Instruments TLC1543IFN, TLC1543IN, TLC1543IDWR, TLC1543IDW, TLC1543IDBLE Datasheet

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TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS052E – MARCH 1992 – OCTOBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10-Bit Resolution A/D Converter

11 Analog Input Channels

Three Built-In Self-Test Modes

Inherent Sample-and-Hold Function

T otal Unadjusted Error...±1 LSB Max

On-Chip System Clock

End-of-Conversion (EOC) Output

T erminal Compatible With TLC542

CMOS Technology

description

The TLC1542C, TLC1542I, TLC1542M, TLC1542Q,

TLC1543C, TLC1543I, and TLC1543Q are CMOS

10-bit switched-capacitor successive-approximation

analog-to-digital converters. These devices have three

inputs and a 3-state output [chip select (CS

input-output clock (I/O CLOCK), address input

(ADDRESS), and data output (DATA OUT)] that

provide a direct 4-wire interface to the serial port of a

host processor. These devices allow high-speed data

transfers from the host.

In addition to a high-speed A/D converter and versatile

control capability, these devices have an on-chip

14-channel multiplexer that can select any one of 11

analog inputs or any one of three internal self-test

voltages. The sample-and-hold function is automatic.

At the end of A /D conversion, the end-of-conversion

(EOC) output goes high to indicate that conversion is

complete. The converter incorporated in the devices

features differential high-impedance reference inputs

that facilitate ratiometric conversion, scaling, and

isolation of analog circuitry from logic and supply noise.

A switched-capacitor design allows low-error conver-

sion over the full operating free-air temperature range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

GND

EOC

I/O CLOCK

ADDRESS

DATA OUT

REF+

REF–

A10

DB, DW, J, OR N PACKAGE

(TOP VIEW)

3 2 1 20 19

910111213

I/O CLOCK

ADDRESS

DATA OUT

REF+

FK OR FN PACKAGE

(TOP VIEW)

A10

REF –

EOC

GND

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS052E – MARCH 1992 – OCTOBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVAILABLE OPTIONS

PACKAGE

SMALL

OUTLINE

(DB)

SMALL OUTLINE

(DW)

CHIP CARRIER

(FN)

PLASTIC DIP

(N)

CHIP CARRIER

(FK)

CERAMIC DIP

(J)

TLC1542CDW TLC1542CFN TLC1542CN

0°C

70°C

TLC1543CDB TLC1543CDW TLC1543CFN TLC1543CN

TLC1542IDW TLC1542IFN TLC1542IN

–

40°C

85°C

TLC1543IDB TLC1543IDW TLC1543IFN TLC1543IN

TLC1542QDB TLC1542QDW TLC1542QFN TLC1542QN

–

40°C

125°C

TLC1543QDB TLC1543QDW TLC1543QFN TLC1543QN

–55°C to 125°C TLC1542MFK TLC1542MJ

functional block diagram

14-Channel

Analog

Multiplexer

REF+ REF–

DATA

OUT

ADDRESS

I/O CLOCK

EOC

A10

14 13

10-Bit

Analog-to-Digital

Converter

(switched capacitors)

Sample and

Hold

Input Address

Self-Test

Reference

Output

Data

System

Clock,

Control Logic,

and I/O

Counters

10-to-1 Data

Selector and

Driver

typical equivalent inputs

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

= 60 pF TYP

(equivalent input

capacitance)

5 MΩ TYP

A0–A10

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS052E – MARCH 1992 – OCTOBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

ADDRESS 17 I Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to

be converted next. The address data is presented with the MSB first and shifts in on the first four rising

edges of I/O CLOCK. After the four address bits have been read into the address register, this input

is ignored for the remainder of the current conversion period.

A0–A10 1–9, 11, 12 I Analog signal inputs. The 11 analog inputs are applied to these terminals and are internally multiplexed.

The driving source impedance should be less than or equal to 1 kΩ.

CS 15 I Chip select. A high-to-low transition on this input resets the internal counters and controls and enables

DATA OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of

the internal system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup

time plus two falling edges of the internal system clock.

DATA OUT 16 O The 3-state serial output for the A/D conversion result. This output is in the high-impedance state when

is high and active when CS is low. With a valid chip select, DATA OUT is removed from the

high-impedance state and is driven to the logic level corresponding to the MSB value of the previous

conversion result. The next falling edge of I/O CLOCK drives this output to the logic level corresponding

to the next most significant bit, and the remaining bits shift out in order with the LSB appearing on the

ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA OUT is driven to a low

logic level so that serial interface data transfers of more than ten clocks produce zeroes as the unused

LSBs.

EOC 19 O End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth I/O

CLOCK and remains low until the conversion is complete and data are ready for transfer.

GND 10 I The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements

are with respect to this terminal.

I/O CLOCK 18 I Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four

functions:

1) It clocks the four input address bits into the address register on the first four rising edges of the I/O

CLOCK with the multiplex address available after the fourth rising edge.

2) On the fourth falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input

begins charging the capacitor array and continues to do so until the tenth falling edge of

I/O CLOCK.

3) It shifts the nine remaining bits of the previous conversion data out on DATA OUT.

4) It transfers control of the conversion to the internal state controller on the falling edge of the tenth

clock.

REF+ 14 I The upper reference voltage value (nominally V

) is applied to this terminal. The maximum input

voltage range is determined by the difference between the voltage applied to this terminal and the

voltage applied to the REF– terminal.

REF– 13 I The lower reference voltage value (nominally ground) is applied to this terminal.

20 I Positive supply voltage

detailed description

With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DA TA OUT

is in the high-impedance state. When the serial interface takes CS

active (low), the conversion sequence begins

with the enabling of I/O CLOCK and ADDRESS and the removal of DA T A OUT from the high-impedance state.

The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O

CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT.

I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface.

The first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired

analog channel, and the next six clocks providing the control timing for sampling the analog input.

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS052E – MARCH 1992 – OCTOBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description (continued)

There are six basic serial-interface timing modes that can be used with the device. These modes are determined

by the speed of I/O CLOCK and the operation of CS

as shown in T able 1. These modes are (1) a fast mode with

a 10-clock transfer and CS

inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer

and CS

active (low) continuously , (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high) between

conversion cycles, (4) a fast mode with a 16-clock transfer and CS

active (low) continuously , (5) a slow mode

with an 11- to 16-clock transfer and CS

inactive (high) between conversion cycles, and (6) a slow mode with

a 16-clock transfer and CS

active (low) continuously.

The MSB of the previous conversion appears at DA TA OUT on the falling edge of CS

in mode 1, mode 3, and

mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the sixteenth clock falling edge in

mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data

are transmitted to the host-serial interface through DATA OUT. The number of serial clock pulses used also

depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On

the tenth clock falling edge, the EOC output goes low and returns to the high logic level when conversion is

complete and the result can be read by the host. Also, on the tenth clock falling edge, the internal logic takes

DA T A OUT low to ensure that the remaining bit values are zero when the I/O CLOCK transfer is more than ten

clocks long.

T able 1 lists the operational modes with respect to the state of CS

, the number of I/O serial transfer clocks that

can be used, and the timing edge on which the MSB of the previous conversion appears at the output.

Table 1. Mode Operation

MODES

NO. OF

I/O CLOCKS

MSB AT DAT A OUT

†

TIMING

DIAGRAM

Mode 1 High between conversion cycles 10 CS falling edge Figure 9

Mode 2 Low continuously 10 EOC rising edge Figure 10

Fast

Modes

Mode 3 High between conversion cycles 11 to 16

‡

CS falling edge Figure 11

Mode 4 Low continuously 16

‡

EOC rising edge Figure 12

Mode 5 High between conversion cycles 11 to 16

‡

CS falling edge Figure 13

Slo

Modes

Mode 6 Low continuously 16

‡

16th clock falling edge Figure 14

†

These edges also initiate serial-interface communication.

‡

No more than 16 clocks should be used.

fast modes

The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is

completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not

begin until the falling edge of the tenth I/O CLOCK.

mode 1: fast mode, CS inactive (high) between conversion cycles, 10-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The

falling edge of CS

begins the sequence by removing DA TA OUT from the high-impedance state. The rising edge

of CS

ends the sequence by returning DA T A OUT to the high-impedance state within the specified delay time.

Also, the rising edge of CS

disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling

edges of the internal system clock.

mode 2: fast mode, CS active (low) continuously, 10-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After

the initial conversion cycle, CS

is held active (low) for subsequent conversions; the rising edge of EOC then

begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous

conversion to appear immediately on this output.

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS052E – MARCH 1992 – OCTOBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

mode 3: fast mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers, and each transfer can be 1 1 to 16 clocks

long. The falling edge of CS

begins the sequence by removing DA T A OUT from the high-impedance state. The

rising edge of CS

ends the sequence by returning DA T A OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS

disables the I/O CLOCK and ADDRESS terminals within a setup time

plus two falling edges of the internal system clock.

mode 4: fast mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS

is held active (low) for subsequent conversions; the rising edge of

EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the

previous conversion to appear immediately on this output.

slow modes

In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow

mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must

occur before the conversion period is complete; otherwise, the device loses synchronization with the host-serial

interface and CS

has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must

occur within 9.5 µs after the tenth I/O clock falling edge.

mode 5: slow mode, CS inactive (high) between conversion cycles, 11- to 16-clock transfer

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 1 1 to 16 clocks

long. The falling edge of CS

begins the sequence by removing DA T A OUT from the high-impedance state. The

rising edge of CS

ends the sequence by returning DA T A OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS

disables the I/O CLOCK and ADDRESS terminals within a setup time

plus two falling edges of the internal system clock.

mode 6: slow mode, CS active (low) continuously, 16-clock transfer

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS

is held active (low) for subsequent conversions. The falling edge of

the sixteenth I/O CLOCK then begins each sequence by removing DA T A OUT from the low state, allowing the

MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next

16-clock transfer initiated by the serial interface.

address bits

The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal

(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address

selects one of 14 inputs (11 analog inputs or three internal test inputs).

analog inputs and test modes

The 11 analog inputs and the three internal test inputs are selected by the 14-channel multiplexer according

to the input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce

input-to-input noise injection resulting from channel switching.

Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six

I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are

applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS052E – MARCH 1992 – OCTOBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

analog inputs and test modes (continued)

Table 2. Analog-Channel-Select Address

ANALOG INPUT

VALUE SHIFTED INTO

ADDRESS INPUT

SELECTED

BINARY HEX

A0 0000 0

A1 0001 1

A2 0010 2

A3 0011 3

A4 0100 4

A5 0101 5

A6 0110 6

A7 0111 7

A8 1000 8

A9 1001 9

A10 1010 A

Table 3. Test-Mode-Select Address

INTERNAL

SELF-TEST

VALUE SHIFTED INTO

ADDRESS INPUT

OUTPUT RESULT

(

HEX

)

‡

VOLTAGE

SELECTED

†

BINARY HEX

OUTPUT

RESULT

(HEX)

‡

ref+

– V

ref–

1011 B 200

ref–

1100 C 000

ref+

1101 D 3FF

†

ref+

is the voltage applied to the REF+ input, and V

ref–

is the voltage applied to the REF–

input.

‡

The output results shown are the ideal values and vary with the reference stability and

with internal offsets.

converter and analog input

The CMOS threshold detector in the successive-approximation conversion system determines each bit by

examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the

conversion process, the analog input is sampled by closing the S

switch and all S

switches simultaneously .

This action charges all the capacitors to the input voltage.

In the next phase of the conversion process, all S

and S

switches are opened and the threshold detector

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF–)

voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and

then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector

looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the

equivalent nodes of all the other capacitors on the ladder are switched to REF–. If the voltage at the summing

node is greater than the trip point of the threshold detector (approximately one-half V

), a 0 bit is placed in

the output register and the 512-weight capacitor is switched to REF–. If the voltage at the summing node is less

than the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains

connected to REF+ through the remainder of the successive-approximation process. The process is repeated

for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS052E – MARCH 1992 – OCTOBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

converter and analog input (continued)

With each step of the successive-approximation process, the initial charge is redistributed among the

capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.

Threshold

Detector

Node 512

REF–

REF+

512

To Output

Latches

REF+REF+ REF+ REF+

124816128256 1

REF+ REF+

REF– REF – REF– REF– REF– REF– REF– REF–

Figure 1. Simplified Model of the Successive-Approximation System

chip-select operation

The trailing edge of CS

starts all modes of operation, and CS can abort a conversion sequence in any mode.

A high-to-low transition on CS

within the specified time during an ongoing cycle aborts the cycle, and the device

returns to the initial state (the contents of the output data register remain at the previous conversion result).

Exercise care to prevent CS

from being taken low close to completion of conversion because the output data

can be corrupted.

reference voltage inputs

There are two reference inputs used with the device: REF+ and REF–. These voltage values establish the upper

and lower limits of the analog input to produce a full-scale and zero reading respectively . The values of REF+,

REF–, and the analog input should not exceed the positive supply or be lower than GND consistent with the

specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher

than REF+ and at zero when the input signal is equal to or lower than REF–.

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS052E – MARCH 1992 – OCTOBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

–0.3 V to V

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

–0.3 V to V

+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Positive reference voltage, V

ref+

+ 0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Negative reference voltage, V

ref–

–0.1 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak input current (any input) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Peak total input current (all inputs) ±30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: TLC1542C, TLC1543C 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . .

TLC1542I, TLC1543I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . .

TLC1542Q, TLC1543Q –40°C to 125°C. . . . . . . . . . . . . . . . . . . . .

TLC1542M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to digital ground with REF– and GND wired together (unless otherwise noted).

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

4.5 5 5.5 V

Positive reference voltage, V

ref+

(see Note 2) V

Negative reference voltage, V

ref–

(see Note 2) 0 V

Differential reference voltage, V

ref+

– V

ref–

(see Note 2) 2.5 V

+0.2 V

Analog input voltage (see Note 2) 0 V

High-level control input voltage, V

= 4.5 V to 5.5 V 2 V

Low-level control input voltage, V

= 4.5 V to 5.5 V 0.8 V

Setup time, address bits at data input before I/O CLOCK↑, t

su(A)

(see Figure 4) 100 ns

Hold time, address bits after I/O CLOCK↑, t

h(A)

(see Figure 4) 0 ns

Hold time, CS low after last I/O CLOCK↓, t

h(CS)

(see Figure 5) 0 ns

Setup time, CS low before clocking in first address bit, t

su(CS)

(see Note 3 and Figure 5) 1.425 µs

Clock frequency at I/O CLOCK (see Note 4) 0 2.1 MHz

Pulse duration, I/O CLOCK high, t

wH(I/O)

190 ns

Pulse duration, I/O CLOCK low, t

wL(I/O)

190 ns

Transition time, I/O CLOCK, t

t(I/O)

(see Note 5 and Figure 6) 1 µs

Transition time, ADDRESS and CS, t

t(CS)

10 µs

TLC1542C, TLC1543C 0 70

TLC1542I, TLC1543I –40 85

Operating

free

air

temperat

TLC1542Q, TLC1543Q –40 125

°C

TLC1542M –55 125

NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1 111111111), while input voltages less than that applied

to REF– convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V

ref+

– V

ref–

); however,

the electrical specifications are no longer applicable.

3. To minimize errors caused by noise at CS

, the internal circuitry waits for a setup time plus two falling edges of the internal system

clock after CS

↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the

minimum CS

setup time has elapsed.

4. For 1 1- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within

9.5 µs.

5. This is the time required for the clock input signal to fall from V

min to V

max or to rise from V

max to V

min. In the vicinity of

normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition

applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

TLC1542C, TLC1542I, TLC1542M, TLC1542Q, TLC1543C, TLC1543I, TLC1543Q

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH

SERIAL CONTROL AND 11 ANALOG INPUTS

SLAS052E – MARCH 1992 – OCTOBER 1998

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range,

= V

ref+

= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP

†

MAX UNIT

= 4.5 V, I

= –1.6 mA 2.4

High

oltage

= 4.5 V to 5.5 V, I

= –20 µA V

–0.1

= 4.5 V, I

= 1.6 mA 0.4

oltage

= 4.5 V to 5.5 V, I

= 20 µA 0.1

Off-state

= V

, CS at V

(hi

mpe

ance-s

)

output current

= 0,

CS at V

–10

High-level input current V

= V

0.005 2.5 µA

Low-level input current V

= 0 –0.005 –2.5 µA

Operating supply current CS at 0 V 0.8 2.5 mA

Selected channel leakage

Selected channel at V

, Unselected channel at 0 V 1

curren

TLC1542/TLC1543

C, I, or Q

Selected channel at 0 V ,

Unselected channel at V

–1

Selected channel at V

= 25°C

Unselected channel at 0 V ,

Selected channel leakage

current TLC1542M

Selected channel at 0 V ,

= 25°C

Unselected channel at V

–1

µA

Selected channel at V

, Unselected channel at 0 V 2.5

Selected channel at 0 V , Unselected channel at V

–2.5

Maximum static analog

reference current into REF+

ref+

= V

, V

ref–

= GND 10 µA

Input

Analog inputs 7

capacitance

Control inputs 5

†

All typical values are at V

= 5 V, T

= 25°C.

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