Texas Instruments TL16C550BFNR, TL16C550BFN, TL16C550BPTR, TL16C550BPT, TL16C550BIPT Datasheet

TL16C550B, TL16C550BI ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996

DCapable of Running With All Existing TL16C450 Software

DAfter Reset, All Registers Are Identical to the TL16C450 Register Set

DIn the FIFO Mode, Transmitter and Receiver Are Each Buffered With 16-Byte FIFOs to Reduce the Number of Interrupts to the CPU

DIn the TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data

DProgrammable Baud Rate Generator Allows

Division of Any Input Reference Clock by 1 to (216 ±1) and Generates an Internal 16 ×

Clock

DStandard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream

DIndependent Receiver Clock Input

DTransmit, Receive, Line Status, and Data Set Interrupts Independently Controlled

description

DFully Programmable Serial Interface Characteristics:

±5-, 6-, 7-, or 8-Bit Characters

±Even-, Odd-, or No-Parity Bit Generation and Detection

±1-, 1 1/2-, or 2-Stop Bit Generation

±Baud Generation (DC to 562 Kbit/s)

DFalse-Start Bit Detection

DComplete Status Reporting Capabilities

D3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Bus and Control Bus

DLine Break Generation and Detection

DInternal Diagnostic Capabilities:

±Loopback Controls for Communications Link Fault Isolation

±Break, Parity, Overrun, Framing Error Simulation

DFully Prioritized Interrupt System Controls

DModem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)

DFaster Plug-In Replacement for National Semiconductor NS16550A

The TL16C550B and the TL16C550BI are functional upgrades of the TL16C450 asynchronous communications element (ACE). Functionally identical to the TL16C450 on power up (character mode² ), the TL16C550B and TL16C550BI can be placed in an alternate mode (FIFO) to relieve the CPU of excessive software overhead.

In this alternate FIFO mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (RXRDY and TXRDY) have been changed to allow signalling of DMA transfers.

The TL16C550B and the TL16C550BI perform serial-to-parallel conversions on data received from a peripheral device or modem and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of the ACE at any point in the ACE operation. Reported status information includes: the type of transfer operation in progress, the status of the operation, and any error conditions encountered.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

² The TL16C550B and the TL16C550BI can also be reset to the TL16C450 mode under software control.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1996, Texas Instruments Incorporated

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

1

TL16C550B, TL16C550BI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996

description (continued)

The TL16C550B and the TL16C550BI ACE include programmable, on-board, baud rate generators. These generators are capable of dividing a reference clock input by divisors from 1 to (216 ±1) and producing a 16× clock for driving the internal transmitter logic. Provisions are included to use this 16×clock to drive the receiver logic. Also included in the ACE is a complete modem control capability and a processor interrupt system that may be software tailored to user requirements to minimize the computing required to handle the communications link.

The TL16C550B is available in a 40-pin DIP (N) package, 44-pin PLCC (FN) package, and 48-pin TQFP (PT) package. The TL16C550BI is available in a 44-pin PLCC (FN) package.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

N PACKAGE (TOP VIEW)

		D0			1	40			VCC
		D1			2	39			RI
		D2			3	38			DCD
		D3			4	37			DSR
		D4			5	36			CTS
		D5			6	35			MR
		D6			7	34			OUT1
		D7			8	33			DTR
RCLK					9	32			RTS
		SIN			10	31			OUT2
SOUT					11	30			INTRPT
		CS0			12	29			RXRDY
		CS1			13	28			A0
		CS2			14	27			A1
BAUDOUT					15	26			A2
		XIN			16	25			ADS
XOUT					17	24			TXRDY
	WR1				18	23			DDIS
	WR2				19	22			RD2
		VSS			20	21			RD1

TL16C550B, TL16C550BI ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996

FN PACKAGE (TOP VIEW)

					D4		D3		D2		D1		D0		NC		V		RI		DCD		DSR		CTS
																	CC
	D5		6			5		4		3		2		1		44			43 42 41 40										MR
				7																				39
	D6																							38					OUT1
				8
	D7																							37					DTR
				9
RCLK																								36					RTS
				10
	SIN			11																				35					OUT2
	NC			12																				34					NC
SOUT				13																				33					INTRPT
	CS0			14																				32					RXRDY
	CS1																							31					A0
				15
																								30					A1
	CS2			16
																								29					A2
BAUDOUT				17
				18 19 20 21 22 23 24 25 26 27 28
					XIN		XOUT		WR1		WR2		V		NC		RD1		RD2 DDIS TXRDY						ADS
													SS

PT PACKAGE (TOP VIEW)

NC

D4 D3

D2

D1

D0

V

RI

DCD

DSR

CTS

NC

CC

NC

48 47 46

45 44 43 42 41 40 39 38 37

NC

1

36

D5

2

35

MR

D6

3

34

OUT1

D7

4

33

DTR

RCLK

5

32

RTS

NC

6

31

OUT2

SIN

7

30

INTRPT

SOUT

8

29

RXRDY

CS0

9

28

A0

CS1

10

27

A1

26

A2

CS2

11

25

NC

BAUDOUT

12

13

14 15 16 17 18 19 20 21 22 23 24

NC

XIN XOUT

WR1

WR2

V

RD1

RD2

NC

DDIS

TXRDY

ADS

SS

NC ± No internal connection

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3

TL16C550B, TL16C550BI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996

functional block diagram

8 ±1

D7 ± D0

28

A0

27

A1

26

A2

12

CS0

13

CS1

14

CS2

25

ADS

35

MR

21

RD1

22

RD2

18

WR1

19

WR2

23

DDIS

24

TXRDY

16

XIN XOUT 17

RXRDY 29

		S
		e
Internal	8	l	Receiver
		e	FIFO
Data Bus
		c
		t
					Receiver	10
Data		Receiver			Shift
						SIN
Bus		Buffer			Register
Buffer		Register
		Line			Receiver	9
					Timing and	RCLK
		Control			Control
		Register
		Divisor
		Latch (LS)	Baud			15
		Divisor	Generator			BAUDOUT
		Latch (MS)
		Line			Line
					Control
		Status
					Register
		Register
Select
			Transmitter
and				S
Control			FIFO	e
Logic		Transmitter		l	Line
				e		11
		Holding		c	Control	SOUT
		Register		t	Register
		Modem				32
						RTS
		Control				36
		Register				CTS
						33
						DTR
		Modem			Modem	37
						DSR
		Status			Control	38
		Register			Logic	DCD
						39
						RI
						34
						OUT1
						31
						OUT2
		Interrupt	Interrupt			30
		Enable	Control			INTRPT
		Register	Logic
		Interrupt
		I/O
		Register
		FIFO
		Control
		Register

Terminal numbers shown are for the N package.

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																									TL16C550B, TL16C550BI
																				ASYNCHRONOUS COMMUNICATIONS ELEMENT
																								SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996
														Terminal Functions
						TERMINAL
	NAME						NO.	NO.	NO.	I/O												DESCRIPTION
							N	FN	PT
	A0						28	31	28	I	Register select. A0 ± A2 are used during read and write operations to select the ACE register to read
	A1						27	30	27		from or write to. Refer to Table 1 for register addresses, and refer to the address strobe (ADS) signal
	A2						26	29	26		description.
							25	28	24	I	Address strobe. When										is active (low), the register select signals (A0, A1, and A2) and chip select
	ADS																		ADS
											signals (CS0, CS1, CS2) drive the internal select logic directly; when high, the register select and chip
											select signals are held in the state they are in when the low-to-high transition of ADS occurs.
							15	17	12	O	Baud out.							is a 16 × clock signal for the transmitter section of the ACE. The clock rate is
	BAUDOUT											BAUDOUT
											established by the reference oscillator frequency divided by a divisor specified by the baud generator
											divisor latches. BAUDOUT can also be used for the receiver section by tying this output to RCLK.
	CS0						12	14	9	I	Chip select. When CS0 = high, CS1 = high, and														= low, these three inputs select the ACE. When
																								CS2
	CS1						13	15	10		any of these inputs are inactive, the ACE remains inactive. Refer to the ADS signal description.
	CS2						14	16	11
							36	40	38	I	Clear to send.					is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of
	CTS												CTS
											the modem status register. Bit 0 (D CTS) of the modem status register indicates that this signal has
											changed states since the last read from the modem status register. If the modem status interrupt is
											enabled when CTS changes state, an interrupt is generated.
	D0						1	2	43	I/O	Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
	D1						2	3	44		information between the ACE and the CPU.
	D2						3	4	45
	D3						4	5	46
	D4						5	6	47
	D5						6	7	2
	D6						7	8	3
	D7						8	9	4
							38	42	40	I	Data carrier detect.									is a modem status signal. Its condition can be checked by reading bit 7 (DCD)
	DCD															DCD
											of the modem status register. Bit 3 (D DCD) of the modem status register indicates that this signal has
											changed states since the last read from the modem status register. If the modem status interrupt is
											enabled when DCD changes state, an interrupt is generated.
	DDIS						23	26	22	O	Driver disable. This output is active (high) when the CPU is not reading data. When active, this output
											can disable an external transceiver.
							37	41	39	I	Data set ready.						is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of
	DSR													DSR
											the modem status register. Bit 1 (D DSR) of the modem status register indicates this signal has changed
											states since the last read from the modem status register. If the modem status interrupt is enabled when
											DSR changes state, an interrupt is generated.
							33	37	33	O	Data terminal ready. When active (low),												informs a modem or data set that the ACE is ready to
	DTR																					DTR
											establish communication. DTR is placed in the active state by setting the DTR bit of the modem control
											register to a high level. DTR is placed in the inactive state either as a result of a master reset, during
											loop mode operation, or clearing the DTR bit.
	INTRPT						30	33	30	O	Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.
											Four conditions that cause an interrupt to be issued are: a receiver error, received data is available or
											timed out (FIFO mode only), the transmitter holding register is empty, or an enabled modem status
											interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result
											of a master reset.
	MR						35	39	35	I	Master reset. When active (high), MR clears most ACE registers and sets the state of various output
											signals. Refer to Table 2.
							34	38	34	O	Outputs 1 and 2. User-designated outputs that are set to their active low states by setting their
	OUT1
	OUT2						31	35	31		respective modem control register bits (OUT1 and OUT2) high. OUT1 and															OUT2	are set to their inactive
											(high) states as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or
											bit 3 (OUT2) of the modem control register.
	RCLK						9	10	5	I	Receiver clock. RCLK is the 16 × baud rate clock for the receiver section of the ACE.

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5

TL16C550B, TL16C550BI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996

Terminal Functions (Continued)

TERMINAL

NAME

NO.

NO.

NO.

I/O

DESCRIPTION

N

FN

PT

21

24

19

I

Read inputs. When either input is active (low or high respectively) while the ACE is selected, the CPU

RD1

RD2

22

25

20

is allowed to read status information or data from a selected ACE register. Only one of these inputs is

required for the transfer of data during a read operation; the other input should be tied in its inactive state

(i.e., RD2 tied low or RD1 tied high).

39

43

41

I

Ring indicator.

is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the

RI

RI

modem status register. Bit 2 (TERI) of the modem status register indicates that the

RI

input has

transitioned from a low to a high state since the last read from the modem status register. If the modem

status interrupt is enabled when this transition occurs, an interrupt is generated.

32

36

32

O

Request to send. When active,

informs the modem or data set that the ACE is ready to receive

RTS

RTS

data. RTS is set to its active state by setting the RTS modem control register bit and is set to its inactive

(high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS)

of the MCR.

29

32

29

O

Receiver ready output. Receiver direct memory access (DMA) signalling is available with this terminal.

RXRDY

When operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO

control register bit 3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed.

Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1

supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO

has been emptied. In DMA mode 0 (FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one

character in the receiver FIFO or receiver holding register, RXRDY is active low. When RXRDY has

been active but there are no characters in the FIFO or holding register, RXRDY goes inactive (high).

In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level or the timeout has been reached, RXRDY

goes active (low); when it has been active but there are no more characters in the FIFO or holding

register, it goes inactive (high).

SIN

10

11

7

I

Serial data input. Input from a connected communications device

SOUT

11

13

8

O

Composite serial data output. Output to a connected communication device. SOUT is set to the marking

(set) state as a result of master reset.

24

27

23

O

Transmitter ready output. Transmitter DMA signalling is available with this terminal. When operating in

TXRDY

the FIFO mode, one of two types of DMA signalling can be selected using FCR3. When operating in

the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a

transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple

transfers are made continuously until the transmit FIFO has been filled.

VCC

40

44

42

5-V supply voltage

VSS

20

22

18

Supply common

18

20

16

I

Write inputs. When either input is active (high or low respectively) and while the ACE is selected, the

WR1

WR2

19

21

17

CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is

required to transfer data during a write operation; the other input should be tied in its inactive state (i.e.,

WR2 tied low or WR1 tied high).

XIN

16

18

14

I/O

External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

XOUT

17

19

15

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TL16C550B, TL16C550BI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . ±0.5 V to 7 V
Input voltage range at any input, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . ±0.5 V to 7 V
Output voltage range, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. ±0.5 V to 7 V
Continuous total power dissipation at (or below) 70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . 300 mW
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±65°C to 150°C
Operating free-air temperature range, TA: TL16C550B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . 0°C to 70°C
TL16C550BI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	±40°C to 85°C
Case temperature for 10 seconds, TC: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N or PT package . . . . . . . .	. . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS (ground).

recommended operating conditions

		MIN	NOM	MAX	UNIT
Supply voltage, VCC		4.75	5	5.25	V
High-level input voltage, VIH		2		VCC	V
Low-level input voltage, VIL		± 0.5		0.8	V
Operating free-air temperature, TA	TL16C550B	0		70	°C
	TL16C550BI	±40		85	°C

electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN TYP²

MAX

UNIT

VOH³

High-level output voltage

IOH = ± 1 mA

2.4

V

VOL³

Low-level output voltage

IOL = 1.6 mA

0.4

V

Il

Input current

VCC = 5.25 V,

VSS = 0,

10

μA

VI = 0 to 5.25 V,

All other terminals floating

IOZ

High-impedance-state output current

VCC = 5.25 V,

VSS = 0,

± 20

μA

VO = 0 to 5.25 V,

Chip selected in write mode or chip deselect

VCC

= 5.

25 V,

TA = 25°C,

SIN,

ICC

Supply current

DSR

, DCD

, CTS, and RI at 2 V,

10

mA

All other inputs at 0.8 V,

XTAL1 at 4 MHz,

No load on outputs,

Baud rate = 50 kbit/s

Ci(CLK)

Clock input capacitance

VCC = 0,

VSS = 0,

15

20

pF

Co(CLK)

Clock output capacitance

20

30

pF

f = 1 MHz,

TA = 25°C,

Ci

Input capacitance

6

10

pF

All other terminals grounded

Co

Output capacitance

10

20

pF

²All typical values are at VCC = 5 V, TA = 25°C.

³These parameters apply for all outputs except XOUT.

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7

TL16C550B, TL16C550BI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996

system timing requirements over recommended ranges of supply voltage and operating free-air temperature

PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN MAX

UNIT

tcR

Cycle time, read (tw7 + td8 + td9)

RC

87

ns

tcW

Cycle time, write (tw6 + td5 + td6)

WC

87

ns

tw1

Pulse duration, clock high

tXH

1

f = 9 MHz maximum

40

ns

tw2

Pulse duration, clock low

tXL

1

f = 9 MHz maximum

40

ns

tw5

Pulse duration, address strobe low

tADS

2,3

9

ns

tw6

Pulse duration, write strobe

tWR

2

40

ns

tw7

Pulse duration, read strobe

tRD

3

40

ns

tw8

Pulse duration, master reset

tMR

1

ms

tsu1

Setup time, address valid before

↑

tAS

2,3

8

ns

ADS

tsu2

Setup time, chip select valid before

↑

tCS

2,3

8

ns

ADS

tsu3

Setup time, data valid before

↓ or WR2↑

tDS

2

15

ns

WR1

th1

Hold time, address low after

↑

tAH

2,3

0

ns

ADS

th2

Hold time, chip select valid after

↑

tCH

2,3

0

ns

ADS

th3

Hold time, chip select valid after

WR1

↑ or WR2↓

tWCS

2

10

ns

th4

Hold time, address valid after

↑ or WR2↓

tWA

2

10

ns

WR1

th5

Hold time, data valid after

WR1

↑ or WR2↓

tDH

2

5

ns

th6

Hold time, chip select valid after

↑ or RD2↓

tRCS

3

10

ns

RD1

th7

Hold time, address valid after

RD1

↑ or RD2↓

tRA

3

20

ns

td4²

Delay time, chip select valid before

↓ or WR2↑

tCSW

2

7

ns

WR1

td5²

Delay time, address valid before

WR1

↓ or WR2↑

tAW

2

7

ns

td6²

Delay time, write cycle,

↑ or WR2↓ to

↓

tWC

2

40

ns

WR1

ADS

td7²

Delay time, chip select valid to

↓ or RD2↑

tCSR

3

7

ns

RD1

td8²

Delay time, address valid to

↓ or RD2↑

tAR

3

7

ns

RD1

↓

td9

Delay time, read cycle,

RD1

↑ or RD2↓ to

ADS

tRC

3

40

ns

td10

Delay time,

↓ or RD2↑ to data valid

tRVD

3

CL = 75 pF

45

ns

RD1

td11

Delay time,

↑ or RD2↓ to floating data

tHZ

3

CL = 75 pF

20

ns

RD1

² Only applies when ADS is low

system switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 2)

PARAMETER			ALT. SYMBOL	FIGURE	TEST CONDITIONS	MIN	MAX	UNIT
tdis(R) Disable time,		↑↓ or RD2↓↑ to DDIS↑↓	tRDD	3	CL = 75 pF	20		ns
	RD1
NOTE 2: Charge and discharge time is determined by VOL, VOH, and external loading.

baud generator switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF

PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

tw3

Pulse duration,

low

tLW

1

f = 9 MHz, CLK ÷2

80

ns

BAUDOUT

tw4

Pulse duration,

high

tHW

1

f = 9 MHz, CLK ÷2

80

ns

BAUDOUT

td1

Delay time, XIN↑ to

↑

tBLD

1

75

ns

BAUDOUT

td2

Delay time, XIN↑↓ to

↓

tBHD

1

65

ns

BAUDOUT

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TL16C550B, TL16C550BI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996

receiver switching characteristics over recommended ranges of supply voltage and operating free-air temperature (see Note 3)

	PARAMETER	ALT. SYMBOL	FIGURE	TEST CONDITIONS	MIN MAX	UNIT
td12	Delay time, RCLK to sample	tSCD	4		10	ns
td13	Delay time, stop to set interrupt or read	tSINT	4,5,6,7,8		1	RCLK
	RBR to LSI interrupt or stop to RXRDY↓					cycle
td14	Delay time, read RBR/LSR to reset interrupt low	tRINT	4,5,6,7,8	CL = 75 pF	40	ns

NOTE 3: In the FIFO mode, the read cycle (RC) = 425 ns (minimum) between reads of the receiver FIFO and the status registers (interrupt identification register or line status register).

transmitter switching characteristics over recommended ranges of supply voltage and operating free-air temperature

	PARAMETER					ALT. SYMBOL	FIGURE	TEST CONDITIONS	MIN	MAX	UNIT
td15	Delay time, initial write (INTRPT low) to transmit					tIRS	9		8	24	baudout
	start (SOUT low)										cycles
td16	Delay time, stop (SOUT low) to interrupt (INTRPT					tSTI	9		8	9	baudout
	high)										cycles
td17	Delay time, WR THR high to reset interrupt					tHR	9	CL = 75 pF		50	ns
	(INTRPT low)
td18	Delay time, initial WR THR low to THRE interrupt					tSI	9		16	32	baudout
	(INTRPT high)										cycles
td19	Delay time, RD IIR low to reset THRE interrupt					tIR	9	CL = 75 pF		35	ns
	(INTRPT low)
	Delay time, WR THR high to			high
td20		TXRDY				tWXI	10,11	CL = 75 pF		35	ns
	(inactive)
	Delay time, start (SOUT low) to				low						baudout
td21			TXRDY			tSXA	10,11	CL = 75 pF		8
	(active)										cycles

modem control switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 75 pF

PARAMETER

ALT. SYMBOL

FIGURE

MIN MAX

UNIT

td22

Delay time, WR MCR low to output

low or high

tMDO

12

50

ns

(RTS,

DTR,

OUT1,

OUT2)

Delay time, modem interrupt

low to set interrupt

td23

(CTS,

DSR,

DCD)

tSIM

12

35

ns

(INTRPT) high

td24

Delay time, RD MSR low to reset interrupt (INTRPT) low

tRIM

12

40

ns

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

9

TL16C550B, TL16C550BI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996

PARAMETER MEASUREMENT INFORMATION

N tw1 tw2

XIN

td1 td2

BAUDOUT (1/1)

td1

td2

BAUDOUT (1/2)

tw3

tw4

BAUDOUT (1/3)

BAUDOUT (1/N)

(N > 3)

2 XIN Cycles

(N ± 2) XIN Cycles

Figure 1. Baud Generator Timing Waveforms

10	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TL16C550B, TL16C550BI

ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136B ± JANUARY 1994 ± REVISED AUGUST 1996

PARAMETER MEASUREMENT INFORMATION

			tw5
ADS	50%		50%		50%
		tsu1
			th1
A0 ± A2	50%	Valid	50%	Valid²	50%
		tsu2
			th2
CS0, CS1, CS2	50%	Valid	Valid²		50%
			th3
		td4	tw6	th4²
		td5			td6
WR1, WR2		50%	Active	50%
		tsu3			th5
D7 ± D0			Valid Data

² Applicable only when ADS is low.

Figure 2. Write Cycle Timing Waveforms

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

11