Texas Instruments TLC1551IFN, TLC1550MJ, TLC1550MFKB, TLC1550IFNR, TLC1550INW Datasheet

				TLC1550I, TLC1550M, TLC1551I
			10-BIT ANALOG-TO-DIGITAL CONVERTERS
					WITH PARALLEL OUTPUTS
				SLAS043C ± MAY 1991 ± REVISED MARCH 1995
D Power Dissipation . . . 40 mW Max				J² OR NW PACKAGE
D	Advanced LinEPIC Single-Poly Process					(TOP VIEW)
	Provides Close Capacitor Matching for			REF+		1		24	RD
	Better Accuracy
				REF ±		2		23	WR
D Fast Parallel Processing for DSP and μP
			ANLG GND			3		22	CLKIN
	Interface
				AIN		4		21	CS
D Either External or Internal Clock Can Be
			ANLG VDD			5		20	D9
	Used		DGTL GND1			6		19	D8
D		μ	DGTL GND2			7		18	D7
	Conversion Time . . . 6 s		DGTL VDD1						D6
D	Total Unadjusted Error . . . ±1 LSB Max					8		17
D	CMOS Technology		DGTL VDD2			9		16	D5
				EOC		10		15	D4
description				D0		11		14	D3
				D1		12		13	D2
	The TLC1550x and TLC1551 are data acquisition		² Refer to the mechanical data for the JW
	analog-to-digital converters (ADCs) using a 10-bit,
			package.
	switched-capacitor,	successive-approximation
				FK OR FN PACKAGE
	network. A high-speed, 3-state parallel port directly
				GND		(TOP VIEW)
	interfaces to a digital signal processor (DSP) or
	microprocessor (μP) system data bus. D0 through			ANLG	REF±	REF+	NC	RD WR	CLKIN
	D9 are the digital output terminals with D0 being the
	least significant bit (LSB). Separate power
	terminals for the	analog and digital portions	AIN	4	3	2	1	28 27 26		CS
	minimize noise pickup in the supply leads.			5					25
			ANLG VDD	6					24	D9
	Additionally, the digital power is divided into two
	parts to separate the lower current logic from the		DGTL GND1	7					23	D8
	higher current bus drivers. An external clock can be		NC	8					22	NC
	applied to CLKIN to override the internal system		DGTL GND2	9					21	D7
	clock if desired.		DGTL VDD1	10					20	D6
	The TLC1550I and TLC1551I are characterized for		DGTL VDD2	11					19	D5
				12 13 14 15 16 17 18
	operation from ±40°C to 85°C. The TLC1550M is			EOC	D0 D1		NC	D2 D3	D4
	characterized over the full military range of ±55°C
	to 125°C.
			NC ± No internal connection

AVAILABLE OPTIONS

			PACKAGE
	TA
		CERAMIC CHIP CARRIER	PLASTIC CHIP CARRIER	CERAMIC DIP	PLASTIC DIP
		(FK)	(FN)	(J)	(NW)
	± 40°C to 85°C	±	TLC1550IFN	±	TLC1550INW
			TLC1551IFN		±
	± 55°C to 125°C	TLC1550MFK	±	TLC1550MJ	±

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or ground.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Advanced LinEPIC is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1995, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

2±1

TLC1550I, TLC1550M, TLC1551I

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS

SLAS043C ± MAY 1991 ± REVISED MARCH 1995

functional block diagram

				EOC
CS	Control		Successive-	10
WR				D0 ± D9
	Logic		Approximation
RD			Register
			10
DGTL	Frequency	Internal		Comp
VDD1	Divided by 2	Clock	10-Bit
	100 kΩ
			Capacitor
	NOM		DAC and S/H
CLKIN	Clock Detector
REF +
REF ±
AIN
typical equivalent inputs
	INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE		INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

AIN

AIN

Ci = 60 pF TYP

(equivalent input 5 MΩ TYP capacitance)

2±2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLC1550I, TLC1550M, TLC1551I 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS

SLAS043C ± MAY 1991 ± REVISED MARCH 1995

Terminal Functions

TERMINAL

DESCRIPTION

NAME

NO.²

NO.³

ANLG GND

4

3

Analog ground. The reference point for the voltage applied on terminals ANLG VDD, AIN, REF+, and REF±.

AIN

5

4

Analog voltage input. The voltage applied to AIN is converted to the equivalent digital output.

ANLG VDD

6

5

Analog positive power supply voltage. The voltage applied to this terminal is designated VDD3.

CLKIN

26

22

Clock input. CLKIN is used for external clocking instead of using the internal system clock. It usually takes a

few microseconds before the internal clock is disabled. To use the internal clock, CLKIN should be tied high

or left unconnected.

25

21

Chip-select.

must be low for

or

to be recognized by the A/D converter.

CS

CS

RD

WR

D0

13

11

Data bus output. D0 is bit 1 (LSB).

D1

14

12

Data bus output. D1 is bit 2.

D2

16

13

Data bus output. D2 is bit 3.

D3

17

14

Data bus output. D3 is bit 4.

D4

18

15

Data bus output. D4 is bit 5.

D5

19

16

Data bus output. D5 is bit 6.

D6

20

17

Data bus output. D6 is bit 7.

D7

21

18

Data bus output. D7 is bit 8.

D8

23

19

Data bus output. D8 is bit 9.

D9

24

20

Data bus output. D9 is bit 10 (MSB).

DGTL GND1

7

6

Digital ground 1. The ground for power supply DGTL VDD1 and is the substrate connection.

DGTL GND2

9

7

Digital ground 2. The ground for power supply DGTL VDD2.

DGTL VDD1

10

8

Digital positive power-supply voltage 1. DGTL VDD1 supplies the logic. The voltage applied to DGTL VDD1 is

designated VDD1.

DGTL VDD2

11

9

Digital positive power-supply voltage 2. DGTL VDD2 supplies only the higher-current output buffers. The voltage

applied to DGTL VDD2 is designated VDD2.

12

10

End-of-conversion.

goes low indicating that conversion is complete and the results have been transferred

EOC

EOC

to the output latch. EOC can be connected to the μP- or DSP-interrupt terminal or can be continuously polled.

28

24

Read input. When

is low and

is taken low, the data is placed on the data bus from the output latch. The

RD

CS

RD

output latch stores the conversion results at the most recent negative edge of EOC. The falling edge of RD

resets EOC to a high within the td(EOC) specifications.

REF+

2

1

Positive voltage-reference input. Any analog input that is greater than or equal to the voltage on REF+ converts

to 1111111111. Analog input voltages between REF + and REF ± convert to the appropriate result in a ratiometric

manner.

REF ±

3

2

Negative voltage reference input. Any analog input that is less than or equal to the voltage on REF ± converts

to 0000000000.

27

23

Write input. When

is low, conversion is started on the rising edge of

On this rising edge, the ADC holds

WR

CS

WR.

the analog input until conversion is completed. Before and after the conversion period, which is given by t conv,

the ADC remains in the sampling mode.

² Terminal numbers for FK and FN packages.

³ Terminal numbers for J and NW packages.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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