Texas Instruments CD74ACT74M96, CD74ACT74M, CD74ACT74E, CD74AC74M96, CD74AC74M Datasheet

[ /Title (CD74 AC74, CD74 ACT74

)

/Subject (Dual D- Type FlipFlop with Set and Reset PositiveEdgeTriggered) /Autho r () /Keywords (Harris Semicon- ductor, Advan ced CMOS , Harris Semicon- ductor, Advan

Data sheet acquired from Harris Semiconductor SCHS231

September 1998

CD74AC74,

CD74ACT74

Dual D-Type Flip-Flop with Set and Reset Positive-Edge-Triggered

Features

•Buffered Inputs

•Typical Propagation Delay (AC00)

- 4.9ns at VCC = 5V, TA = 25oC, CL = 50pF

•Exceeds 2kV ESD Protection MIL-STD-883, Method 3015

•SCR-Lachup-Resistant CMOS Process and Circuit Design

Description

The Harris CD74AC74 and CD74ACT74 dual D-type, positive edge triggered flip-flops use the Harris ADVANCED CMOS technology. These flip-flops have independent DATA, SET, RESET, and CLOCK inputs and Q and Q outputs. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. SET and RESET are independent of the clock and are accomplished by a low level at the appropriate input.

•Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption

•Balanced Propagation Delays

•AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply

•±24mA Output Drive Current

-Fanout to 15 FAST™ ICs

-Drives 50Ω Transmission Lines

Ordering Information

PART	TEMP.		PKG.
NUMBER	RANGE (oC)	PACKAGE	NO.
CD74AC74E	0 to 70, -40 to 85	14 Ld PDIP	E14.3
	-55 to 125
CD74ACT74E	0 to 70, -40 to 85	14 Ld PDIP	E14.3
	-55 to 125
CD74AC74EX	0 to 70, -40 to 85	14 Ld PDIP	E14.3
	-55 to 125
CD74ACT74EX	0 to 70, -40 to 85	14 Ld PDIP	E14.3
	-55 to 125
CD74AC74M	0 to 70, -40 to 85	14 Ld SOIC	M14.15
	-55 to 125
CD74ACT74M	0 to 70, -40 to 85	14 Ld SOIC	M14.15
	-55 to 125
NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local sales office or Harris customer service for ordering information.

Pinout

CD74AC74, CD74ACT74

(PDIP, SOIC)

TOP VIEW

	1R		1		14		VCC
	1D
			2		13		2R
1CP							2D
			3		12
							2CP
	1S		4		11
	1Q
			5		10		2S
							2Q
	1Q		6		9
GND
			7		8		2Q

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.		File Number 1881.1
FAST™ is a Trademark of Fairchild Semiconductor.	1
Copyright © Harris Corporation 1998

CD74AC74, CD74ACT74

Functional Diagram

1

1R

2

R

5

1D

D

1Q

3

FF1

6

CP

1CP

1Q

4

S

1S

13

2R

12

R

9

2D

D

2Q

11

FF2

8

CP

2CP

2Q

10

S

2S

TRUTH TABLE

INPUTS

OUTPUTS

CP

D

Q

SET

RESET

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H (Note 5)

H (Note 5)

H

H

−

H

H

L

H

H

−

L

L

H

H

H

L

X

Q0

Q0

NOTES:

3.H = High level (steady state), L = Low level (steady state), X = Don’t care, − = Transition from Low to High level.

4.Q0 = the level of Q before the indicated input conditions were established.

5.This configuration is nonstable, that is, it will not persist when set and reset inputs return to their inactive (high) level.

2

CD74AC74, CD74ACT74

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 6V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±50mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±50mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC or IGND (Note 6) . . . . . .	. . .±100mA

Thermal Information
Thermal Resistance (Typical, Note 8)	θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 175
Maximum Junction Temperature (Plastic Package) . . .	. . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . . . 300oC

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 7)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

6.For up to 4 outputs per device, add ±25mA for each additional output.

7.Unless otherwise specified, all voltages are referenced to ground.

8.θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST					-40oC TO		-55oC TO
		CONDITIONS		VCC	25oC		85oC		125oC
PARAMETER	SYMBOL	VI (V)	IO (mA)	(V)	MIN	MAX	MIN	MAX	MIN	MAX	UNITS
AC TYPES
High Level Input Voltage	VIH	-	-	1.5	1.2	-	1.2	-	1.2	-	V
				3	2.1	-	2.1	-	2.1	-	V
				5.5	3.85	-	3.85	-	3.85	-	V
Low Level Input Voltage	VIL	-	-	1.5	-	0.3	-	0.3	-	0.3	V
				3	-	0.9	-	0.9	-	0.9	V
				5.5	-	1.65	-	1.65	-	1.65	V
High Level Output Voltage	VOH	VIH or VIL	-0.05	1.5	1.4	-	1.4	-	1.4	-	V
			-0.05	3	2.9	-	2.9	-	2.9	-	V
			-0.05	4.5	4.4	-	4.4	-	4.4	-	V
			-4	3	2.58	-	2.48	-	2.4	-	V
			-24	4.5	3.94	-	3.8	-	3.7	-	V
			-75	5.5	-	-	3.85	-	-	-	V
			(Note 9, 10)
			-50	5.5	-	-	-	-	3.85	-	V
			(Note 9, 10)

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