TLV5614 2.7-V TO 5.5-V 12-BIT 3- S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 ± SEPTEMBER 1998
DFour 12-Bit D/A Converters
DProgrammable Settling Time of Either 3 µs or 9 µs Typ
DTMS320, (Q)SPI, and Microwire Compatible Serial Interface
DInternal Power-On Reset
DLow Power Consumption:
8 mW, Slow Mode ± 5-V Supply
3.6 mW, Slow Mode ± 3-V Supply
DReference Input Buffer
DVoltage Output Range . . . 2 × the Reference
Input Voltage
DMonotonic Over Temperature
description
DDual 2.7-V to 5.5-V Supply (Separate Digital and Analog Supplies)
DHardware Power Down (10 nA)
DSoftware Power Down (10 nA)
DSimultaneous Update
applications
DBattery Powered Test Instruments
DDigital Offset and Gain Adjustment
DIndustrial Process Controls
DMachine and Motion Control Devices
DCommunications
DArbitrary Waveform Generation
D OR PW PACKAGE
(TOP VIEW)
The TLV5614 is a quadruple 12-bit voltage output |
DVDD |
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AVDD |
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digital-to-analog converter (DAC) with a flexible |
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4-wire serial interface. The 4-wire serial interface |
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PD |
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REFINAB |
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allows glueless interface to TMS320, SPI, QSPI, |
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LDAC |
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14 |
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OUTA |
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and Microwire serial ports. The TLV5614 is |
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DIN |
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OUTB |
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programmed with a 16-bit serial word comprised |
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SCLK |
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OUTC |
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of a DAC address, individual DAC control bits, and |
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CS |
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OUTD |
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a 12-bit DAC value. The device has provision for |
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FS |
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10 |
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REFINCD |
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two supplies: one digital supply for the serial |
DGND |
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AGND |
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interface (via pins DVDD and DGND), and one for |
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the DACs, reference buffers, and output buffers (via pins AVDD and AGND). Each supply is independent of the other, and can be any value between 2.7 V and 5.5 V. The dual supplies allow a typical application where the DAC will be controlled via a microprocessor operating on a 3 V supply (also used on pins DVDD and DGND), with the DACs operating on a 5 V supply. Of course, the digital and anlog supplies can be tied together.
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. A rail-to-rail output stage and a power-down mode makes it ideal for single voltage, battery based applications. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFINAB and REFINCD terminals to reduce the need for a low source impedance drive to the terminal. REFINAB and REFINCD allow DACs A and B to have a different reference voltage then DACs C and D.
The TLC5614 is implemented with a CMOS process and is available in a 16-terminal SOIC package. The TLV5614C is characterized for operation from 0°C to 70°C. The TLV5614I is characterized for operation from ±40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
1 |
TLV5614
2.7-V TO 5.5-V 12-BIT 3- S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 ± SEPTEMBER 1998
AVAILABLE OPTIONS
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PACKAGE |
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TA |
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SOIC |
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TSSOP |
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(D) |
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(PW) |
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0°C to 70°C |
TLV5614CD |
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TLV5614CPW |
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± 40°C to 85°C |
TLV5614ID |
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TLV5614IPW |
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functional block diagram |
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AVDD |
DVDD |
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REFINAB |
15 |
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1 |
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DAC A |
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Power-On |
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Reset |
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OUTA |
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12 |
12-Bit |
10 |
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DAC |
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14-Bit |
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Latch |
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Data |
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and |
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Control |
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2-Bit |
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Register |
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Control |
2 |
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Serial |
14 |
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Data |
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Power-Down/ |
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DIN |
Input |
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Latch |
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Speed Control |
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Register |
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2 |
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FS |
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DAC Select/ |
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5 |
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SCLK |
Control |
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DAC B |
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OUTB |
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CS |
Logic |
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DAC C |
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12 |
OUTC |
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REFINCD |
10 |
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DAC D |
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11 |
OUTD |
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3 |
2 |
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AGND |
DGND |
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LDAC |
PD |
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2 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TLV5614 2.7-V TO 5.5-V 12-BIT 3- S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 ± SEPTEMBER 1998
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Terminal Functions |
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TERMINAL |
I/O |
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DESCRIPTION |
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NAME |
NO. |
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AGND |
9 |
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Analog ground |
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AVDD |
16 |
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Analog supply |
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I |
Chip select. This terminal is active low. |
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CS |
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DGND |
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Digital ground |
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DIN |
4 |
I |
Serial data input |
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DVDD |
1 |
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Digital supply |
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FS |
7 |
I |
Frame sync input. The falling edge of the frame sync pulse indicates the start of a serial data frame shifted out to |
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the TLV5614. |
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2 |
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Power down pin. Powers down all DACs (overriding their individual power down settings), and all output stages. |
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PD |
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This terminal is active low. |
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3 |
I |
Load DAC. When the |
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signal is high, no DAC output updates occur when the input digital data is read into |
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LDAC |
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LDAC |
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the serial interface. The DAC outputs are only updated when LDAC is low. |
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REFINAB |
15 |
I |
Voltage reference input for DACs A and B. |
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REFINCD |
10 |
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Voltage reference input for DACs C and D. |
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SCLK |
5 |
I |
Serial Clock input |
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OUTA |
14 |
O |
DACA output |
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OUTB |
13 |
O |
DACB output |
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OUTC |
12 |
O |
DACC output |
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OUTD |
11 |
O |
DACD output |
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²
Supply voltage, (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . . . . 7 |
V |
Supply voltage difference, (AVDD to DVDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±2.8 V to 2.8 |
V |
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.3 V to DVDD + 0.3 |
V |
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
±0.3 V to AVDD + 0.3 |
V |
Operating free-air temperature range, TA: TLV5614C . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . . . 0°C to 70°C |
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TLV5614I . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . . ±40°C to 85°C |
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Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
. . . . . . ±65°C to 150°C |
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Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . |
. . . . . . . . . . . . . . 260°C |
²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
3 |
TLV5614
2.7-V TO 5.5-V 12-BIT 3- S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 ± SEPTEMBER 1998
recommended operating conditions
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MIN |
NOM |
MAX |
UNIT |
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Supply voltage, AVDD, DVDD |
5-V supply |
4.5 |
5 |
5.5 |
V |
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3-V supply |
2.7 |
3 |
3.3 |
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High-level digital input, VIH |
DVDD = 2.7 V to 5.5 V |
2 |
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V |
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Low-level digital input, VIL |
DVDD = 2.7 V to 5.5 V |
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0.8 |
V |
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Reference voltage, Vref to REFINAB, REFINCD terminal |
5-V supply, See Note 1 |
0 |
2.048 |
VDD±1.5 |
V |
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3-V supply, See Note 1 |
0 |
1.024 |
VDD±1.5 |
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Load resistance, RL |
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kΩ |
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Load capacitance, CL |
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100 |
pF |
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Serial clock rate, SCLK |
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20 |
MHz |
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Operating free-air temperature |
TLV5614C |
0 |
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70 |
°C |
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TLV5614I |
±40 |
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85 |
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NOTE 1: Voltages greater than AVDD/2 will cause output saturation for large DAC codes.
electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)
static DAC specifications
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PARAMETER |
TEST CONDITIONS |
MIN TYP |
MAX |
UNIT |
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Resolution |
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12 |
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bits |
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Integral nonlinearity (INL), end point adjusted |
See Note 2 |
±1.5 |
±4 |
LSB |
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Differential nonlinearity (DNL) |
See Note 3 |
±0.5 |
±1 |
LSB |
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EZS |
Zero scale error (offset error at zero scale) |
See Note 4 |
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±12 |
mV |
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Zero scale error temperature coefficient |
See Note 5 |
10 |
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ppm/°C |
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EG |
Gain error |
See Note 6 |
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±0.6 |
% of FS |
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voltage |
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Gain error temperature coefficient |
See Note 7 |
10 |
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ppm/°C |
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PSRR |
Power supply rejection ratio |
Zero scale |
See Notes 8 and 9 |
± 80 |
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Full scale |
± 80 |
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NOTES: 2. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.
3.The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
4.Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
5.Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) ± EZS (Tmin)]/Vref × 106/(Tmax ± Tmin).
6.Gain error is the deviation from the ideal output (2 Vref ± 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
7.Gain temperature coefficient is given by: EG TC = [EG(Tmax) ± EG (Tmin)]/Vref × 106/(Tmax ± Tmin).
8.Zero-scale-error rejection ratio (EZS±RR) is measured by varying the AVDD from 5 ± 0.5 V and 3 ± 0.5 V dc, and measuring the proportion of this signal imposed on the zero-code output voltage.
9.Full-scale rejection ratio (EG-RR) is measured by varying the AVDD from 5 ± 0.5 V and 3 ± 0.5 V dc and measuring the proportion of this signal imposed on the full-scale output voltage after subtracting the zero scale change.
4 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TLV5614 2.7-V TO 5.5-V 12-BIT 3- S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 ± SEPTEMBER 1998
supply
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PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
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VO |
Voltage output range |
RL = 10 kΩ |
0 |
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AVDD±0.4 |
V |
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Output load regulation accuracy |
RL = 2 kΩ vs 10 kΩ |
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0.1 |
0.25 |
% of FS |
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voltage |
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PARAMETER |
TEST CONDITIONS |
MIN TYP |
MAX |
UNIT |
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VI |
Input voltage range |
See Note 10 |
0 |
AVDD±1.5 |
V |
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RI |
Input resistance |
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10 |
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MΩ |
CI |
Input capacitance |
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pF |
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Reference feed through |
REFIN = 1 Vpp at 1 kHz + 1.024 V dc |
±75 |
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Reference input bandwidth |
REFIN = 0.2 Vpp + 1.024 V dc large signal |
Slow |
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Fast |
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Reference input voltages greater than VDD/2 will cause output saturation for large DAC codes.
11.Reference feedthrough is measured at the DAC output with an input code = 000 hex and a Vref (REFINAB or REFINCD) input = 1.024 Vdc + 1 Vpp at 1 kHz.
digital inputs (DIN, CS, LDAC, PD)
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PARAMETER |
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TEST CONDITIONS |
MIN TYP |
MAX |
UNIT |
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IIH |
High-level digital input current |
VI = VDD |
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µA |
IIL |
Low-level digital input current |
VI = 0 V |
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±1 |
µA |
CI |
Input capacitance |
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3 |
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pF |
power supply
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PARAMETER |
TEST CONDITIONS |
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MIN TYP |
MAX |
UNIT |
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5-V supply, |
Slow |
1.6 |
2.4 |
mA |
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No load, Clock running, |
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Fast |
3.8 |
5.6 |
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IDD |
Power supply current |
All inputs 0 V or VDD |
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3-V supply, |
Slow |
1.2 |
1.8 |
mA |
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No load, Clock running, |
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Fast |
3.2 |
4.8 |
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All inputs 0 V or DVDD |
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Power down supply current (see Figure 12) |
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POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
5 |
TLV5614
2.7-V TO 5.5-V 12-BIT 3- S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 ± SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) (continued)
analog output dynamic performance
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PARAMETER |
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TEST CONDITIONS |
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MIN TYP |
MAX |
UNIT |
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SR |
Output slew rate |
CL = 100 pF, |
RL = 10 kΩ, |
Fast |
5 |
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VO = 10% to 90%, |
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Slow |
1 |
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V/µs |
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Vref = 2.048 V, 1024 V |
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ts |
Output settling time |
To ± 0.5 LSB, |
CL = 100 pF, |
Fast |
3 |
5.5 |
µs |
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RL = 10 kΩ, |
See Notes 12 and 14 |
Slow |
9 |
20 |
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ts(c) |
Output settling time, code to code |
To ± 0.5 LSB, |
CL = 100 pF, |
Fast |
1 |
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µs |
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RL = 10 kΩ, |
See Note 15 |
Slow |
2 |
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Glitch energy |
Code transition from 7FF to 800 |
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10 |
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SNR |
Signal-to-noise ratio |
Sinewave generated by DAC, |
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74 |
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Reference voltage = 1.024 at 3 V and 2.048 at 5 V, |
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S/(N+D) |
Signal to noise + distortion |
66 |
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fs = 400 KSPS, |
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dB |
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THD |
Total harmonic Distortion |
fOUT = 1.1 kHz sinewave, |
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CL = 100 pF, |
RL = 10 kΩ, |
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SFDR |
Spurious free dynamic range |
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BW = 20 kHz |
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NOTES: 12. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change ofFFF hex to 080 hex for 080 hex to FFF hex.
13.Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change of one count.
14.Limits are ensured by design and characterization, but are not production tested.
6 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TLV5614 2.7-V TO 5.5-V 12-BIT 3- S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 ± SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted) (continued)
digital input timing requirements
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MIN NOM MAX |
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tsu(CS±FS) |
Setup time, |
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low before FS↓ |
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CS |
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tsu(FS±CK) |
Setup time, FS low before first negative SCLK edge |
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tsu(C16±FS) |
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising |
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edge of FS |
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Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before |
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CS |
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tsu(C16±CS) |
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup |
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twH |
Pulse duration, SCLK high |
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twL |
Pulse duration, SCLK low |
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tsu(D) |
Setup time, data ready before SCLK falling edge |
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th(D) |
Hold time, data held valid after SCLK falling edge |
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twH(FS) |
Pulse duration, FS high |
20 |
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PARAMETER MEASUREMENT INFORMATION
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twL |
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twH |
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SCLK |
1 |
2 |
3 |
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5 |
15 |
16 |
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tsu(D) |
th(D) |
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DIN |
D15 |
D14 |
D13 |
D12 |
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D1 |
D0 |
tsu(FS-CK)
tsu(C16-CS)
tsu(CS-FS)
CS
twH(FS) |
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tsu(C16-FS) |
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FS
Figure 1. Timing Diagram
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
7 |
TLV5614
2.7-V TO 5.5-V 12-BIT 3- S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 ± SEPTEMBER 1998
TYPICAL CHARACTERISTICS
VO ± Output ± V
LOAD REGULATION |
LOAD REGULATION |
0.2 |
VDD = 3 V, |
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0.18 |
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Vref = 1 V, |
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0.16 |
VO = Full Scale |
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0.14 |
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0.25 |
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3 V Slow Mode, Sink |
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0.12 |
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0.20 |
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Output± |
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0.10 |
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3 V Fast Mode, Sink |
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0.08 |
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0.15 |
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0.06 |
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0.10 |
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0.04 |
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0.02 |
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0.05 |
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0 |
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0.01 |
0.02 |
0.05 |
0.1 |
0.2 |
0.5 |
1 |
2 |
0 |
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Load Current ± mA |
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VDD = 5 V, |
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Vref = 2 V, |
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VO = Full Scale |
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5 V Slow Mode, Sink |
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5 V Fast Mode, Sink |
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0 |
0.02 |
0.04 |
0.1 |
0.2 |
0.4 |
1 |
2 |
4 |
Load Current ± mA
Figure 2 |
Figure 3 |
LOAD REGULATION |
LOAD REGULATION |
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4.01 |
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2.001 |
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5 V Slow Mode, Source |
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2.001 |
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4.005 |
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2.000 |
± V |
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± V |
2.000 |
4 |
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1.999 |
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5 V Fast Mode, Source |
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1.999 |
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3.995 |
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O |
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O 1.998 |
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1.998 |
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3.99 |
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VDD = 5 V, |
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1.997 |
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Vref = 2 V, |
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1.997 |
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VO = Full Scale |
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3.985 |
0.02 |
0.04 |
0.1 |
0.2 |
0.4 |
1 |
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4 |
1.996 |
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Load Current ± mA |
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3 V Slow Mode, Source |
3 V Fast Mode, Source |
VDD = 3 V, |
Vref = 1 V, |
VO = Full Scale |
0 |
0.01 |
0.02 0.05 |
0.1 |
0.2 |
0.5 |
1 |
2 |
Load Current ± mA
Figure 4 |
Figure 5 |
8 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
TLV5614 2.7-V TO 5.5-V 12-BIT 3- S QUADRUPLE DIGITAL-TO-ANALOG CONVERTERS
WITH POWER DOWN
SLAS188 ± SEPTEMBER 1998
TYPICAL CHARACTERISTICS
SUPPLY CURRENT |
SUPPLY CURRENT |
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vs |
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vs |
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TEMPERATURE |
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TEMPERATURE |
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4 |
VDD = 3 V, |
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3.5 |
Vref = 1.024 V, |
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3.5 |
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VO Full Scale |
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Fast Mode |
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mA |
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mA |
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3 |
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Fast Mode |
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± |
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Current |
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Current |
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Vref = 1.024 V, |
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Supply± |
2.5 |
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Supply± |
2.5 |
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VDD = 5 V, |
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VO Full Scale |
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DD |
1.5 |
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DD |
1.5 |
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I |
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I |
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1 |
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Slow Mode |
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1 |
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Slow Mode |
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0.5 |
±55 |
±40 |
±25 |
0 |
25 |
40 |
70 |
85 |
125 |
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0.5 |
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85 |
125 |
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±55 |
±40 |
±25 |
0 |
25 |
40 |
70 |
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T ± Temperature ± °C |
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T ± Temperature ± °C |
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Figure 6 |
Figure 7 |
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TOTAL HARMONIC DISTORTION |
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TOTAL HARMONIC DISTORTION |
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vs |
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vs |
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FREQUENCY |
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FREQUENCY |
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0 |
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±10 |
Vref = 1 V dc + 1 V p/p Sinewave, |
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Vref = 1 V dc + 1 V p/p Sinewave, |
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HarmonicTotal±THD Distortion ± dB |
Output Full Scale |
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HarmonicTotal±THD Distortion ± dB |
±10 |
Output Full Scale |
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±70 |
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±20 |
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±20 |
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±30 |
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±30 |
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±±40 |
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±±40 |
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±50 |
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±50 |
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±60 |
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Fast Mode |
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±60 |
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Slow Mode |
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±70 |
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±80 |
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50 |
100 |
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±80 |
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5 |
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50 |
100 |
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0 |
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f ± Frequency ± kHz |
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f ± Frequency ± kHz |
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Figure 8 |
Figure 9 |
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265 |
9 |