Texas Instruments TLV5613IPWR, TLV5613IPW, TLV5613IDW, TLV5613CPWR, TLV5613CPW Datasheet

TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A ± DECEMBER 1997 ± REVISED JULY 1998

D12-Bit Voltage Output DAC

DSingle Supply 2.7-V to 5.5-V Operation

DSeparate Analog and Digital Supplies

D±0.4 LSB Differential Nonlinearity (DNL),

±1.5 LSB Integral Nonlinearity (INL)

DProgrammable Settling Time vs Power

Consumption:

1 s/4.2 mW in Fast Mode,

3.5s/1.2 mW in Slow Mode

D8-Bit Controller Compatible Interface (8+4

Bit)

DPower-Down Mode (50 nW)

applications

DDigital Servo Control Loops

DBattery Powered Test Instruments

DDigital Offset and Gain Adjustment

DIndustrial Process Control

DSpeech Synthesis

DMachine and Motion Control Devices

DMass Storage Devices

DW OR PW PACKAGE

(TOP VIEW)

DRail-to-Rail Output Buffer

DSynchronous or Asynchronous Update

DMonotonic Over Temperature

description

The TLV5613 is a 12-bit voltage output digital-to-analog converter (DAC) with a 8-bit microcontroller compatible parallel interface. The 8 LSBs, the 4 MSBs and 3 control bits are written using three different addresses. Developed for a wide range of supply voltages, the TLV5613 can be operated from 2.7 V to 5.5 V.

D2				1	20					D1
D3				2	19					D0
D4				3	18					CS
D5				4	17					WE
D6				5	16
										LDAC
D7				6	15					PWD
A1				7	14					GND
A0				8	13					OUT
SPD				9	12					REF
DVDD				10	11					AVDD

The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class A (slow mode: AB) output stage to improve stability and reduce settling time. The programmable settling time of the DAC allows the designer to optimize speed versus power dissipation. The settling time can be chosen by the control bits within the 16-bit data word.

Implemented with a CMOS process, the device is designed for single supply operation from 2.7 V to 5.5 V. It is available in 20 pin SOIC in standard commercial and industrial temperature ranges.

AVAILABLE OPTIONS

PACKAGE

	TA	SMALL OUTLINE	TSSOP
		(DW)	(PW)
	0°C to 70°C	TLV5613CDW	TLV5613CPW
	± 40°C to 85°C	TLV5613IDW	TLV5613IPW

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 1998, Texas Instruments Incorporated

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1

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A ± DECEMBER 1997 ± REVISED JULY 1998

functional block diagram

REF

SPD

PWD

			Powerdown
	Power-On
			and Speed
	Reset		Control

	2	3		2		x2	OUT
A(0±1)			3-Bit
			Control
		Interface	Latch
CS
		Control
WE		4	4-Bit	4	12	12
						12-Bit
			DAC MSW			DAC
			Holding
						Latch
			Latch
		8	8-Bit	8
			DAC LSW
			Holding
			Latch
D(0±7)	8
					LDAC

Terminal Functions

					TERMINAL		I/O	DESCRIPTION
					NAME	NO.
	AVDD					11		Analog positive power supply
	A0					8	I	Address input
	A1					7	I	Address input
						18	I	Chip select. Digital input active low, used to enable/disable inputs
	CS
	DVDD					10		Digital positive power supply
	D0 (LSB) ± D7 (MSB)					1±6, 19, 20	I	Data input
						16	I	Load DAC. Digital input active low, used to load DAC output
	LDAC
	OUT					13	O	DAC analog voltage output
						15	I	Power down. Digital input active low
	PWD
	REF					12	I	Analog reference voltage input
	SPD					9	I	Speed select. Digital input
	GND					14		Ground
						17	I	Write enable. Digital input active low, used to latch data
	WE

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A ± DECEMBER 1997 ± REVISED JULY 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)²

Supply voltage (DVDD, AVDD to GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . 7	V
Supply voltage difference, AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ± 2.8 V to 2.8	V
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	± 0.3 V to AVDD + 0.3	V
Digital input voltage range to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	± 0.3 V to DVDD + 0.3	V
Operating free-air temperature range, TA: TLV5613C . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . 0°C to 70°C
TLV5613I . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . ±40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

			MIN	NOM	MAX	UNIT
	Supply voltage, VDD	5-V Supply	4.5	5	5.5	V
		3-V Supply	2.7	3	3.3
	Supply voltage difference, VDD = AVDD ± DVDD		±2.8	0	2.8	V
	Power on reset, POR		0.55		2	V
	High-level digital input voltage, VIH	DVDD = 2.7 V to 5.5 V	2			V
	Low-level digital input voltage, VIL	DVDD = 2.7 V to 5.5 V			0.8	V
	Reference voltage, Vref to REFIN terminal	5-V Supply (see Note 1)	GND	2.048	AVDD ± 1.5	V
		3-V Supply (see Note 1)	GND	1.024	AVDD ± 1.5
	Load resistance, RL		2			kΩ
	Load capacitance, CL				100	pF
	Operating free-air temperature, TA	TLV5613C	0		70	°C
		TLV5613I	± 40		85	°C

NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ (VDD ± 0.4)/2 causes clipping of the transfer function.

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3

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A ± DECEMBER 1997 ± REVISED JULY 1998

electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VDD = 5 V

Fast

1.6

3

mA

No load,

Slow

0.5

1.3

mA

IDD

Power supply current

All inputs = GND or DVDD,

Fast

1.4

2.7

mA

DAC latch = 0x800

VDD = 3 V

Slow

0.4

1.1

mA

Power down supply current

See Figure 14

0.01

10

µA

PSRR

Power supply rejection ratio

Zero scale,

See Note 2

±65

dB

Full scale,

See Note 3

±65

NOTES: 2. Power supply rejection ratio at zero scale is measured by varying AVDD and is given by:

PSRR = 20 log [(EZS(AVDDmax) ± EZS(AVDDmin))/AVDDmax]

3. Power supply rejection ratio at full scale is measured by varying AVDD and is given by:

PSRR = 20 log [(EG(AVDDmax) ± EG(AVDDmin))/AVDDmax]

static DAC specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

Vref(REFIN) = 2.048 V, 1.024 V

12

bits

Integral nonlinearity (INL), end point adjusted

Vref(REFIN) = 2.048 V, 1.024 V,

See Note 4

± 1.5

± 4

LSB

Differential nonlinearity (DNL)

Vref(REFIN) = 2.048 V, 1.024 V,

See Note 5

± 0.4

± 1

LSB

EZS

Zero-scale error (offset error at zero scale)

Vref(REFIN) = 2.048 V, 1.024 V,

See Note 6

± 3

± 20

mV

Zero-scale-error temperature coefficient

Vref(REFIN) = 2.048 V, 1.024 V,

See Note 7

3

ppm/°C

EG

Gain error

Vref(REFIN) = 2.048 V, 1.024 V,

See Note 8

± 0.25

± 0.5

% of FS

voltage

Gain error temperature coefficient

Vref(REFIN) = 2.048 V, 1.024 V,

See Note 9

1

ppm/°C

NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors.

5.The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

6.Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

7.Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) ± EZS (Tmin)]/Vref × 106/(Tmax ± Tmin).

8.Gain error is the deviation from the ideal output (Vref ± 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.

9.Gain temperature coefficient is given by: EG TC = [EG(Tmax) ± EG (Tmin)]/Vref × 106/(Tmax ± Tmin).

output specifications

	PARAMETER	TEST CONDITIONS		MIN TYP	MAX	UNIT
VO	Output voltage	RL = 10 kΩ		0	AVDD±0.4	V
	Output load regulation accuracy	VO(OUT) = 4.096 V,	RL = 2 kΩ,	0.1	0.29	% of FS
						voltage
IOSC(source)	Output short circuit source current	VO(OUT) = 0 V, input all 1s	AVDD = 5 V	±100		mA
			AVDD = 3 V	±25
IOSC(sink)	Output short circuit sink current	RL = 100 Ω, input all 1s	AVDD = 5 V	±10		mA
			AVDD = 3 V	±10

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A ± DECEMBER 1997 ± REVISED JULY 1998

electrical characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

reference input (REFIN)

	PARAMETER	TEST CONDITIONS		MIN TYP	MAX	UNIT
Vref	Input voltage reference	See Note 10		0	AVDD± 1.5	V
Ri	Input resistance			10		MΩ
Ci	Input capacitance			5		pF
	Reference input bandwidth	REF = 0.2 Vpp + 1.024 V dc	Fast mode	1.6		MHz
			Slow mode	1		MHz
	Reference feed through	REF = 1 Vpp at 1 kHz + 1.024 V dc,		±60		dB
		See Note 10
NOTES: 10. Reference feedthrough is measured at the DAC output with an input code = 0x000.

digital inputs

	PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
IIH	High-level digital input current	VI = DVDD				1	µA
IIL	Low-level digital input current	VI = 0 V		±1			µA
Ci	Input capacitance				8		pF

operating characteristics over recommended operating free-air temperature range, supply voltages, and reference voltages (unless otherwise noted)

analog output dynamic performance

	PARAMETER	TEST CONDITIONS			MIN	TYP	MAX	UNIT
ts(FS)	Output settling time, full scale	RL = 10 kΩ,	See Note 11	Fast		1	3	µs
		CL = 100 pF,		Slow		3.5	7
ts(CC)	Output settling time, code-to-code	RL = 10 kΩ,	See Note 12	Fast		0.5	1.5	µs
		CL = 100 pF,		Slow		1	2
SR	Slew rate	RL = 10 kΩ,	See Note 13	Fast		8		V/µs
				Slow		1.5
		CL = 100 pF,
	Glitch energy	Code-to-code transition				1		nV±s
S/N	Signal-to-noise				65	78
S/(N+D)	Signal-to-noise + distortion	fs = 480 KSPS,	fout = 1 kHz,		58	69		dB
THD	Total harmonic distortion	RL = 10 k,	CL = 100 pF			±68	±60
	Spurious free dynamic range				60	72

NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0x3FF or 0x3FF to 0x020.

12.Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. The max time applies to code changes near zero scale or full scale.

13.Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.

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5

TLV5613

2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A ± DECEMBER 1997 ± REVISED JULY 1998

timing requirements

digital inputs

MIN NOM MAX

UNIT

tsu(D)

Setup time, data ready before positive

edge

9

ns

WE

tsu(CS-WE)

Setup time,

CS

low before positive

WE

edge

13

ns

tsu(A)

Setup time, address bits A0, A1

17

ns

th(D)

Hold time, data held after positive

edge

0

ns

WE

tsu(WE-LD)

Setup time, positive

WE

edge before

LDAC

low

0

ns

tw(WE)

Pulse duration,

high

10

ns

WE

tw(LD)

Pulse duration,

low

10

s

LDAC

PARAMETER MEASUREMENT INFORMATION

D(0±7)	X	Data	X
A(0±1)	X	Address	X
		tsu(D)
CS		tsu(A)	th(D)
		tsu(CS-WE)	tw(WE)
WE
		tsu(WE-LD)	tw(LD)

LDAC

Figure 1. Timing Diagram

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TLV5613 2.7 V TO 5.5 V 12-BIT PARALLEL DIGITAL-TO-ANALOG CONVERTER WITH POWER DOWN

SLAS174A ± DECEMBER 1997 ± REVISED JULY 1998

PARAMETER MEASUREMENT INFORMATION

D(0±7)	X	MSW	X	LSW	X
A(0±1)	X	0	X	1	X
CS
WE

LDAC

Figure 2. Example of a Complete Write Cycle Using LDAC to Update the DAC

D(0±7)	X	MSW	X	LSW	X	Control	X
A(0±1)	X	0	X	1	X	3	X
CS

WE

LDAC

Figure 3. Example of a Complete Write Cycle Using the Control Word to Update the DAC

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