Texas Instruments CD74ACT174M96, CD74ACT174M, CD74ACT174E, CD74AC174M96, CD74AC174M Datasheet

CD74AC174,

CD54/74ACT174

Data sheet acquired from Harris Semiconductor SCHS241A

September 1998 - Revised May 2000

Hex D Flip-Flop with Reset

[ /Title	Features				Description
	•	Buffered Inputs
(CD74					The CD74AC174 and ’ACT174 are hex D flip-flops with reset
AC174	•	Typical Propagation Delay			that utilize Advanced CMOS Logic technology. Information at
					the D input is transferred to the Q output on the positive-
,		- 6.4ns at VCC = 5V, TA = 25oC, CL = 50pF
					going edge of the clock pulse. All six flip-flops are controlled
CD74	•	Exceeds 2kV ESD Protection MIL-STD-883, Method			by a common clock (CP) and a common reset (MR). Reset-
ACT17		3015			ting is accomplished by a low voltage level independent of
4	•	SCR-Latchup-Resistant CMOS Process and Circuit			the clock.
)		Design			Ordering Information
/Sub-	•	Speed of Bipolar FAST™/AS/S with Significantly
ject		Reduced Power Consumption				PART	TEMP.
(Hex D	•	Balanced Propagation Delays			NUMBER		RANGE (oC)	PACKAGE
Flip-	•	AC Types Feature 1.5V to 5.5V Operation and			CD74AC174E		-55 to 125	16 Ld PDIP
Flop					CD74AC174M		-55 to 125	16 Ld SOIC
		Balanced Noise Immunity at 30% of the Supply
with	•	±24mA Output Drive Current			CD54ACT174F3A		-55 to 125	16 Ld CERDIP
Reset)					CD74ACT174E		-55 to 125	16 Ld PDIP
		-	Fanout to 15 FAST™ ICs
/Autho
		-	Drives 50Ω Transmission Lines		CD74ACT174M		-55 to 125	16 Ld SOIC
r ()					NOTES:
/Key-					1. When ordering, use the entire part number. Add the suffix 96 to
words					obtain the variant in the tape and reel.
(Har-					2. Wafer and die for this part number is available which meets all elec-
ris					trical specifications. Please contact your local TI sales office or cus-
					tomer service for ordering information.
Semi-
con-	Pinout
ductor,				CD54ACT174
Advan
					(CERDIP)
ced			CD74AC174, CD74ACT174
CMOS				(PDIP, SOIC)
				TOP VIEW
, Harris
Semi-			MR	1	16 VCC
con-
			Q0	2	15 Q5
ductor,			D0	3	14 D5
Advan			D1	4	13 D4
ced			Q1	5	12 Q4
TTL)			D2	6	11 D3
/Cre-			Q2	7	10	Q3
ator ()			GND	8	9	CP
/DOCI
NFO

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

	FAST™ is a Trademark of Fairchild Semiconductor.	1
	Copyright © 2000, Texas Instruments Incorporated

CD74AC174, CD54/74ACT174

Functional Diagram

	9
	CP	CP	2
	3	D
	D0		Q0
		R
	4		5
	D1		Q1
	6		7
	D2		Q2
	11		10
	D3		Q3
	13		12
	D4		Q4
	14		15
	D5		Q5
	1
	MR		GND = 8
			VCC = 16

TRUTH TABLE (EACH FLIP-FLOP)

			INPUTS		OUTPUTS
RESET			CLOCK	DATA
			CP	Dn	Qn
	(MR)
	L		X	X	L
	H		↑	H	H
	H		↑	L	L
	H		L	X	Q0

H = High Level (Steady State)

L = Low Level (Steady State) X = Irrelevant

↑ = Transition from Low to High level

Q0 = Level before the Indicated Steady-State Input conditions were established.

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CD74AC174, CD54/74ACT174

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 6V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±50mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±50mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . .	. . .±100mA

Thermal Information
Thermal Resistance (Typical, Note 5)	θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 90
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 160
Maximum Junction Temperature (Plastic Package) . . .	. . . . . . 1505oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . . . 300oC
(SOIC - Lead Tips Only)

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3.For up to 4 outputs per device, add ±25mA for each additional output.

4.Unless otherwise specified, all voltages are referenced to ground.

5.θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST					-40oC TO		-55oC TO
		CONDITIONS		VCC	25oC		85oC		125oC
PARAMETER	SYMBOL	VI (V)	IO (mA)	(V)	MIN	MAX	MIN	MAX	MIN	MAX	UNITS
AC TYPES
High Level Input Voltage	VIH	-	-	1.5	1.2	-	1.2	-	1.2	-	V
				3	2.1	-	2.1	-	2.1	-	V
				5.5	3.85	-	3.85	-	3.85	-	V
Low Level Input Voltage	VIL	-	-	1.5	-	0.3	-	0.3	-	0.3	V
				3	-	0.9	-	0.9	-	0.9	V
				5.5	-	1.65	-	1.65	-	1.65	V
High Level Output Voltage	VOH	VIH or VIL	-0.05	1.5	1.4	-	1.4	-	1.4	-	V
			-0.05	3	2.9	-	2.9	-	2.9	-	V
			-0.05	4.5	4.4	-	4.4	-	4.4	-	V
			-4	3	2.58	-	2.48	-	2.4	-	V
			-24	4.5	3.94	-	3.8	-	3.7	-	V
			-75	5.5	-	-	3.85	-	-	-	V
			(Note 6, 7)
			-50	5.5	-	-	-	-	3.85	-	V
			(Note 6, 7)

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