Texas Instruments CD74ACT245SM96, CD74ACT245SM, CD74ACT245M96, CD74ACT245M, CD74ACT245E Datasheet

Data sheet acquired from Harris Semiconductor SCHS245

September 1998

CD74AC245,

CD74ACT245

Octal-Bus Transceiver,

Three-State, Non-Inverting

Features

Description

•

Buffered Inputs

The CD74AC245 and CD74ACT245 are octal-bus transceiv-

•

Typical Propagation Delay

ers that utilize the Harris Advanced CMOS Logic technology.

They are non-inverting three-state bidirectional transceiver-

-

4ns at V

= 5V, T = 25oC, C

= 50pF

L

buffers intended for two-way transmission from “A” bus to “B”

CC

A

•

Exceeds 2kV ESD Protection MIL-STD-883, Method

bus or “B” bus to “A”. The logic level present on the direction

input (DIR) determines the data direction. When the output

3015

enable input (OE) is HIGH, the outputs are in the high-

• SCR-Latchup-Resistant CMOS Process and Circuit

impedance state.

[ /Title

Design

Ordering Information

(CD74

•

Speed of Bipolar FAST™/AS/S with Significantly

AC245

Reduced Power Consumption

PART

TEMP.

PKG.

PACKAGE

,

•

Balanced Propagation Delays

NUMBER

RANGE (oC)

NO.

CD74AC245E

-55 to 125

20 Ld PDIP

E20.3

CD74

•

AC Types Feature 1.5V to 5.5V Operation and

CD74ACT245E

-55 to 125

20 Ld PDIP

E20.3

ACT24

Balanced Noise Immunity at 30% of the Supply

CD74AC245M

-55 to 125

20 Ld SOIC

M20.3

5)

• ±24mA Output Drive Current

CD74ACT245M

-55 to 125

20 Ld SOIC

M20.3

/Sub-

-

Fanout to 15 FAST™ ICs

ject

-

Drives 50Ω Transmission Lines

CD74AC245SM

-55 to 125

20 Ld SSOP

M20.15

CD74ACT245SM

-55 to 125

20 Ld SSOP

M20.15

(Octal-

Bus

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to

Trans-

obtain the variant in the tape and reel.

ceiver,

2. Wafer and die for this part number is available which meets all elec-

Three-

trical specifications. Please contact your local sales office or Harris

State,

customer service for ordering information.

Non-

Invert-

Pinout

ing)

CD74AC245, CD74ACT245

/Autho

(PDIP, SSOP, SOIC)

r ()

TOP VIEW

/Key-

words

DIR

1

20

VCC

(Har-

A0

2

19 OE

A1

3

18

B0

ris

A2

4

17

B1

Semi-

A3

5

16

B2

con-

A4

6

15

B3

ductor,

A5

7

14

B4

Advan

A6

8

13

B5

ced

A7

9

12

B6

CMOS

GND

10

11 B7

, Harris

Semi-

con-

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

File Number 1907.1

	FAST™ is a Trademark of Fairchild Semiconductor.	1
	Copyright © Harris Corporation 1998

CD74AC245, CD74ACT245

Functional Diagram

	2	18
	A0	B0
	3	17
	A1	B1
	4	16
	A2	B2
	5	15
	A3	B3
	6	14
	A4	B4
	7	13
	A5	B5
	8	12
	A6	B6
	9	11
	A7	B7
	DIR	1
		19
	OE
	TRUTH TABLE
CONTROL INPUTS
OE	DIR	OPERATION
L	L	B Data to A Bus
L	H	A Data to B Bus
H	X	Isolation

H = High Level, L = Low Level, X = Irrelevant

To prevent excess currents in the High-Z (isolation) modes, all I/O terminals should be terminated with 10kΩ to 1MΩ resistors.

2

CD74AC245, CD74ACT245

Absolute Maximum Ratings

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . .	-0.5V to 6V
DC Input Diode Current, IIK	±20mA
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . .
DC Output Diode Current, IOK	±50mA
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . .
DC Output Source or Sink Current per Output Pin, IO	±50mA
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
DC VCC or Ground Current, ICC or IGND (Note 3) . . . . . .	. . .±100mA

Thermal Information
Thermal Resistance (Typical, Note 5)	θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 125
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 120
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .	. 130
Maximum Junction Temperature (Plastic Package) . . .	. . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .	-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . .	. . . . . . . 300oC

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V . . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3.For up to 4 outputs per device, add ±25mA for each additional output.

4.Unless otherwise specified, all voltages are referenced to ground.

5.θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

		TEST					-40oC TO		-55oC TO
		CONDITIONS		VCC	25oC		85oC		125oC
PARAMETER	SYMBOL	VI (V)	IO (mA)	(V)	MIN	MAX	MIN	MAX	MIN	MAX	UNITS
AC TYPES
High Level Input Voltage	VIH	-	-	1.5	1.2	-	1.2	-	1.2	-	V
				3	2.1	-	2.1	-	2.1	-	V
				5.5	3.85	-	3.85	-	3.85	-	V
Low Level Input Voltage	VIL	-	-	1.5	-	0.3	-	0.3	-	0.3	V
				3	-	0.9	-	0.9	-	0.9	V
				5.5	-	1.65	-	1.65	-	1.65	V
High Level Output Voltage	VOH	VIH or VIL	-0.05	1.5	1.4	-	1.4	-	1.4	-	V
			-0.05	3	2.9	-	2.9	-	2.9	-	V
			-0.05	4.5	4.4	-	4.4	-	4.4	-	V
			-4	3	2.58	-	2.48	-	2.4	-	V
			-24	4.5	3.94	-	3.8	-	3.7	-	V
			-75	5.5	-	-	3.85	-	-	-	V
			(Note 6, 7)
			-50	5.5	-	-	-	-	3.85	-	V
			(Note 6, 7)

3