Texas Instruments TPS75133QPWP, TPS75125QPWPR, TPS75125QPWP, TPS75118QPWP, TPS75118QPWPR Datasheet

TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS241 ± MARCH 2000

D 1.5-A Low-Dropout Voltage Regulator

PWP PACKAGE

D Available in 1.5-V, 1.8-V, 2.5-V, 3.3-V, Fixed

(TOP VIEW)

Output and Adjustable Versions

GND/HEATSINK

1

20

GND/HEATSINK

D Open Drain Power-Good (PG) Status

NC

2

19

NC

Output (TPS751xxQ)

IN

3

18

NC

D Open Drain Power-On Reset With 100-ms

IN

4

17

GND

NC

Delay (TPS753xxQ)

EN

5

16

D Dropout Voltage Typically 160 mV at 1.5 A

PG or RESET²

6

15

NC

FB/SENSE

7

14

NC

(TPS75133Q)

OUTPUT

8

13

NC

D Ultra Low 75 A Typical Quiescent Current

9

12

NC

OUTPUT

D Fast Transient Response

GND/HEATSINK

10

11

GND/HEATSINK

D2% Tolerance Over Specified Conditions

	For Fixed-Output Versions	NC ± No internal connection
D	20-Pin TSSOP (PWP) PowerPAD Package	² PG is on the TPS751xx and	RESET	is on the TPS753xx
D	Thermal Shutdown Protection

description

The TPS753xxQ and TPS751xxQ are low dropout regulators with integrated power-on reset and power-good (PG) functions respectively. These devices are capable of supplying 1.5 A of output current with a dropout of 160 mV (TPS75133Q, TPS75333Q). Quiescent current is 75 A at full load and drops down to 1 A when the device is disabled. TPS751xxQ and TPS753xxQ are designed to have fast transient response for larger load current changes.

TPS75x33Q

DROPOUT VOLTAGE

vs	TPS75x15Q
JUNCTION TEMPERATURE	LOAD TRANSIENT RESPONSE

	300
					in		mV	50
	250				± Change		Voltage ±
± mV								0
	200		IO = 1.5 A
Voltage					O		Output	±50
					V
	150							±100
Dropout
	100					± A		±150
±						Current
DO			IO = 0.5 A					1.5
V
	50					± Output
	0						O	0
		10	60	110	160	I
	±40
		TJ ± Junction Temperature ± °C

					IL=1.5 A
					CL=100 F (Tantalum)
					VO=1.5 V
0	1	2	3	4	5	6	7	8	9	10
				t ± Time ± ms

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2000, Texas Instruments Incorporated

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1

TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS241 ± MARCH 2000

description (continued)

Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 160 mV at an output current of 1.5 A for the TPS75x33Q) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 75 A over the full range of output current, 1 mA to 1.5 A). These two key specifications yield a significant improvement in operating life for battery-powered systems.

The device is enabled when EN is connected to a low level voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN (enable) shuts down the regulator, reducing the quiescent current to less than 1 A at TJ = 25°C.

For the TPS751xxQ, the power-good terminal (PG) is an active high, open drain output, which can be used to implement a power-on reset or a low-battery indicator.

The RESET (SVS, POR, or power on reset) output of the TPS753xxQ initiates a reset in microcomputer and microprocessor systems in the event of an undervoltage condition. An internal comparator in the TPS753xxQ monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When the output reaches 95% of its regulated voltage, RESET goes to a high-impedance state after a 100-ms delay. RESET goes to a logic-low state when the regulated output voltage is pulled below 95% (i.e., over load condition) of its regulated voltage.

The TPS751xxQ or TPS753xxQ is offered in 1.5-V, 1.8-V, 2.5-V and 3.3-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges. The TPS751xxQ and TPS753xxQ families are available in 20-pin TSSOP (PWP) packages.

AVAILABLE OPTIONS

TJ	OUTPUT VOLTAGE	TSSOP (PWP)
	(TYP)	PG		RESET
	3.3 V	TPS75133QPWP	TPS75333QPWP
	2.5 V	TPS75125QPWP	TPS75325QPWP
± 40°C to 125°C
	1.8 V	TPS75118QPWP	TPS75318QPWP
	1.5 V	TPS75115QPWP	TPS75315QPWP
	Adjustable 1.5 V to 5 V	TPS75101QPWP	TPS75301QPWP

NOTE: The TPS75x01 is programmable using an external resistor divider (see application information). The PWP package is available taped and reeled. Add an R suffix to the device type (e.g., TPS75201QPWPR) to indicate tape and reel.

	VI	3	PG or	6	PG or RESET Output
		IN	RESET
		4		7
			SENSE
		IN
			OUT	8	VO
	0.22 F	5		9
			OUT
		EN			CO²
				+
			GND	47	F
		17

² See application information section for capacitor selection details.

Figure 1. Typical Application Configuration (For Fixed Output Options)

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS241 ± MARCH 2000

functional block diagramÐadjustable version

IN
EN
	PG or RESET
_
+	OUT

	+	100 ms Delay	R1
	_	(for RESET Option)
	Vref = 1.1834 V		FB

R2

GND

External to the device

functional block diagramÐfixed-voltage version

	IN
	EN
			PG or RESET
	_
	+		OUT
	+	100 ms Delay	SENSE
			R1
	_	(for RESET Option)
	Vref = 1.1834 V

R2

GND

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS241 ± MARCH 2000

					Terminal Functions (TPS751xxQ)
		TERMINAL		I/O		DESCRIPTION
		NAME	NO.
			5	I		Enable Input
	EN
	FB/SENSE		7	I		Feedback input voltage for adjustable device (sense input for fixed options)
	GND		17			Regulator Ground
	GND/HEATSINK		1, 10, 11, 20			Ground/heatsink
	IN		3, 4	I		Input voltage
	NC		2, 12, 13, 14,			No connection
			15, 16, 18, 19
	OUTPUT		8, 9	O		Regulated output voltage
	PG		6	O		Power good output

						Terminal Functions (TPS753xxQ)
			TERMINAL		I/O		DESCRIPTION
		NAME		NO.
				5	I		Enable Input
	EN
	FB/SENSE			7	I		Feedback input voltage for adjustable device (sense input for fixed options)
	GND			17			Regulator Ground
	GND/HEATSINK			1, 10, 11, 20			Ground/heatsink
	IN			3, 4	I		Input voltage
	NC			2, 12, 13, 14,			No connection
				15, 16, 18, 19
	OUTPUT			8, 9	O		Regulated output voltage
				6	O		Reset output
	RESET

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS241 ± MARCH 2000

TPS753xxQ RESET timing diagram

Vres

(see Note A)

VI
						Vres
						t
VO	V	IT +	(see Note B)	V	IT +	(see Note B)

Threshold

Voltage

Less than 5% of the

VIT ±

VIT ± (see Note B)

output voltage

(see Note B)

		t
RESET	100 ms	100 ms
Output
	Delay	Delay
Output		Output
Undefined		Undefined
		t

NOTES: A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor symbology.

B. VIT ±Trip voltage is typically 5% lower than the output voltage (95%VO) VIT± to VIT+ is the hysteresis voltage.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS241 ± MARCH 2000

TPS751xxQ PG timing diagram

VPG

(see Note A)

VI
				VPG
				t
VO	V	(see Note B)	V	(see Note B)
		IT +		IT +

Threshold

Voltage

VIT ±(see Note B)

VIT ±(see Note B)

	t
PG
Output
Output	Output
Undefined	Undefined
	t

NOTES: A. VPG is the minimum input voltage for a valid PG. The symbol VPG is not currently listed within EIA or JEDEC standards for semiconductor symbology.

B. VIT ±Trip voltage is typically 17% lower than the output voltage (83%VO) VIT± to VIT+ is the hysteresis voltage.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS241 ± MARCH 2000

absolute maximum ratings over operating junction temperature range (unless otherwise noted)

Input voltage range³ , VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . ±0.3 V to 5.5 V
Voltage range at		EN		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . ±0.3 V to 16.5 V
Maximum PG voltage (TPS751xxQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . 16.5 V
Maximum	RESET		. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .voltage (TPS753xxQ)		. . . . . . . . . . . . . . . . . . 16.5 V
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					See dissipation rating tables
Output voltage, VO (OUTPUT, FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . 5.5 V
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . ±40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . ±65°C to 150°C
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .					. . . . . . . . . . . . . . . . . . . . 2 kV

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ³ All voltage values are with respect to network terminal ground.

DISSIPATION RATING TABLE 1 ± FREE-AIR TEMPERATURES

	PACKAGE	AIR FLOW	TA < 25°C	DERATING FACTOR	TA = 70°C	TA = 85°C
		(CFM)	POWER RATING	ABOVE TA = 25°C	POWER RATING	POWER RATING
	PWP§	0	2.9 W	23.5 mW/°C	1.9 W	1.5 W
		300	4.3 W	34.6 mW/°C	2.8 W	2.2 W
	PWP¶	0	3 W	23.8 mW/°C	1.9 W	1.5 W
		300	7.2 W	57.9 mW/°C	4.6 W	3.8 W

§This parameter is measured with the recommended copper heat sink pattern on a 1-layer PCB, 5-in × 5-in PCB, 1 oz. copper, 2-in × 2-in coverage (4 in2).

¶This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5-in × 2-in PCB, 1 oz. copper with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer to TI technical brief SLMA002.

recommended operating conditions

	MIN	MAX	UNIT
Input voltage, VI#	2.7	5	V
Output voltage range, VO	1.5	5	V
Output current, IO (see Note 1)	0	1.5	A
Operating virtual junction temperature, TJ (see Note 1)	± 40	125	°C

# To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

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TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS241 ± MARCH 2000

electrical characteristics over recommended operating junction temperature range (TJ = ±40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 47 F (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Adjustable

1.5 V ≤ VO ≤ 5 V,

TJ = 25°C

VO

Voltage

1.5 V ≤ VO ≤ 5 V

0.98 VO

1.02 VO

1.5 V Output

TJ = 25°C,

2.7 V < VIN < 5 V

1.5

2.7 V < VIN < 5 V

1.470

1.530

Output voltage

1.8 V Output

TJ = 25°C,

2.8 V < VIN < 5 V

1.8

V

(see Notes 1 and 3)

2.8 V < VIN < 5 V

1.764

1.836

2.5 V Output

TJ = 25°C,

3.5 V < VIN < 5 V

2.5

3.5 V < VIN < 5 V

2.450

2.550

3.3 V Output

TJ = 25°C,

4.3 V < VIN < 5 V

3.3

4.3 V < VIN < 5 V

3.234

3.366

Quiescent current (GND current) (see Note 2)

TJ = 25°C,

See Note 3

75

µA

See Note 3

125

Output voltage line regulation (

VO/VO)

VO + 1 V < VI ≤ 5 V,

TJ = 25°C

0.01

(see Notes 1 and 2)

%/V

Output voltage line regulation (

VO/VO)

VO + 1 V < VI < 5 V

0.1

(see Notes 1 and 2)

Load regulation (see Note 3)

1

mV

Output noise voltage

BW = 300 Hz to 50 kHz, VO = 1.5 V

60

µVrms

CO = 100 µF,

TJ = 25°C

Output current Limit

VO = 0 V

3.3

4.5

A

Thermal shutdown junction temperature

150

°C

= VI,

TJ = 25°C,

1

µA

Standby current

EN

µA

EN = VI

10

FB input current

TPS75x01Q

FB = 1.5 V

±1

1

µA

High level enable input voltage

2

V

Low level enable input voltage

0.7

V

Power supply ripple rejection (see Note 2)

f = 100 Hz,

CO = 100 µF,

63

dB

TJ = 25°C,

See Note 1, IO = 1.5 A

Minimum input voltage for valid

IO(PG) = 300µA,

V(PG) ≤ 0.8 V

1

1.3

V

PG

PG

Trip threshold voltage

VO decreasing

80

86

%VO

(TPS751xxQ)

Hysteresis voltage

Measured at VO

0.5

%VO

Output low voltage

VI = 2.7 V,

IO(PG) = 1mA

0.15

0.4

V

Leakage current

V(PG) = 5 V

1

µA

NOTES: 1. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 5 V.

2.

If VO ≤ 1.8 V then Vimin = 2.7 V, Vimax = 5 V:

VO Vimax *

2.7 V

Line Reg. (mV) + % V

1000

100

If VO ≥ 2.5 V then Vimin = VO + 1 V, Vimax = 5 V:

Line Reg. (mV) + % V

VO Vimax * VO ) 1 V

1000

100

3.

IO = 1 mA to 1.5 A

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TPS75101Q, TPS75115Q, TPS75118Q, TPS75125Q, TPS75133Q WITH POWER GOOD TPS75301Q, TPS75315Q, TPS75318Q, TPS75325Q, TPS75333Q WITH RESET FAST-TRANSIENT-RESPONSE 1.5-A LOW-DROPOUT VOLTAGE REGULATORS

SLVS241 ± MARCH 2000

electrical characteristics over recommended operating junction temperature range (TJ = ±40°C to 125°C), VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, CO = 47 F (unless otherwise noted) (continued)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Minimum input voltage for valid

RESET

IO(RESET) = 300 A,

V(RESET) ≤ 0.8 V

1.1

1.3

V

Trip threshold voltage

VO decreasing

92

98

%VO

Reset

Hysteresis voltage

Measured at VO

0.5

%VO

(TPS753xxQ)

Output low voltage

IO(RESET) = 1 mA

0.15

0.4

V

Leakage current

V(RESET) = 5.5 V

1

A

RESET time-out delay

100

ms

±1

1

A

Input current (EN)

EN

= VI

A

EN = 0 V

±1

0

1

High level

input voltage

2

V

EN

Low level

input voltage

0.7

V

EN

IO = 1.5 A,

VI = 3.2 V,

160

Dropout voltage, (3.3 V output) (see Note 4)

TJ = 25°C

mV

IO = 1.5 A,

VI = 3.2 V

300

NOTE 4: IN voltage equals VO(Typ) ± 100 mV; TPS75x15Q, TPS75x18Q and TPS75x25Q dropout voltage limited by input voltage range limitations (i.e., TPS75x33Q input voltage needs to drop to 3.2 V for purpose of this test).

Table of Graphs

				FIGURE
	VO	Output voltage	vs Output current	2,	3
			vs Junction temperature	4,	5
		Ground current	vs Junction temperature	6
		Power supply ripple rejection	vs Frequency	7
		Output spectral noise density	vs Frequency	8
	Zo	Output impedance	vs Frequency	9
	VDO	Dropout voltage	vs Input voltage	10
			vs Junction temperature	11
		Line transient response		12,	14
		Load transient response		13,	15
	VO	Output voltage	vs Time	16
		Equivalent series resistance (ESR)	vs Output current	18,	19

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