Texas Instruments TPS7201QD, TPS7201QDR, TPS7248QD, TPS7233QPWR, TPS7233QPWLE Datasheet

TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q

TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998

DAvailable in 5-V, 4.85-V, 3.3-V, 3.0-V, 2.75-V§, and 2.5-V Fixed-Output and Adjustable Versions

DDropout Voltage <85 mV Max at IO = 100 mA (TPS7250)

DLow Quiescent Current, Independent of Load, 180 μA Typ

D, P, OR PW PACKAGE

(TOP VIEW)

SENSE² /FB³				1	8		OUT
RESET/PG				2	7		OUT
GND				3	6		IN
							IN
	EN			4	5

D 8-Pin SOIC and 8-Pin TSSOP Package

² SENSE ± Fixed voltage options only

D Output Regulated to ± 2% Over Full

(TPS7225, TPS7228§, TPS7230, TPS7233,

TPS7248, and TPS7250)

Operating Range for Fixed-Output Versions

³ FB ± Adjustable version only (TPS7201)

D Extremely Low Sleep-State Current,

0.5 μA Max

600

D Power-Good (PG) Status Output

TA = 25°C

description

± mV

500

The TPS72xx family of low-dropout (LDO) voltage

TPS7225

regulators offers the benefits of low-dropout

Voltage

400

TPS7230

voltage, micropower operation, and miniaturized

packaging. These regulators feature extremely

300

± Dropout

low dropout voltages and quiescent currents

TPS7233

compared to conventional LDO regulators.

200

TPS7248

Offered in small-outline integrated-circuit (SOIC)

packages and 8-terminal thin shrink small-outline

DO

(TSSOP), the TPS72xx series devices are ideal

V

100

for cost-sensitive designs and for designs where

TPS7250

board space is at a premium.

0

A combination of new circuit design and process

50

100

150

200

250

innovation has enabled the usual pnp pass

0

IO ± Output Current ± mA

transistor to be replaced by a PMOS device.

Because the PMOS pass element behaves as a

Figure 1. Typical Dropout Voltage Versus

low-value resistor, the dropout voltage is very low

Output Current

± maximum of 85 mV at 100 mA of load current

(TPS7250) ± and is directly proportional to the

load current (see Figure 1). Since the PMOS pass

element is a voltage-driven device, the quiescent current is very low (300 μA maximum) and is stable over the entire range of output load current (0 mA to 250 mA). Intended for use in portable systems such as laptops and cellular phones, the low-dropout voltage and micropower operation result in a significant increase in system battery operating life.

The TPS72xx also features a logic-enabled sleep mode to shut down the regulator, reducing quiescent current to 0.5 μA maximum at TJ = 25°C. Other features include a power-good function that reports low output voltage and may be used to implement a power-on reset or a low-battery indicator.

The TPS72xx is offered in 2.5-V, 2.75-V§, 3-V, 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2% over line, load, and temperature ranges (3% for adjustable version).

§ This device is in the product preview stage of development. Please contact the local TI sales office for availability.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

This document contains information on products in more than one phase	Copyright 1998, Texas Instruments Incorporated
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
POST OFFICE BOX 655303 •DALLAS, TEXAS 75265	1

TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q

TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY

MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998

AVAILABLE OPTIONS

	OUTPUT VOLTAGE				PACKAGED DEVICES
		(V)						CHIP FORM
TJ
	MIN	TYP	MAX	SMALL OUTLINE		PDIP	TSSOP	(Y)
				(D)		(P)	(PW)
	4.9	5	5.1	TPS7250QD		TPS7250QP	TPS7250QPWR	TPS7250Y
	4.75	4.85	4.95	TPS7248QD		TPS7248QP	TPS7248QPWR	TPS7248Y
	3.23	3.3	3.37	TPS7233QD		TPS7233QP	TPS7233QPWR	TPS7233Y
±55°C to 150°C	2.94	3	3.06	TPS7230QD		TPS7230QP	TPS7230QPWR	TPS7230Y
	2.69	2.75	2.81	TPS7228QD²		TPS7228QP²	TPS7228QPWR²	TPS7228Y²
	2.45	2.5	2.55	TPS7225QD		TPS7225QP	TPS7225QPWR	TPS7225Y
		Adjustable		TPS7201QD		TPS7201QP	TPS7201QPWR	TPS7201Y
	1.2 V to 9.75 V

The D package is available taped and reeled. Add R suffix to device type (e.g., TPS7250QDR). The PW package is only available left-end taped and reeled. The TPS7201Q is programmable using an external resistor divider (see application information). The chip form is tested at 25°C.

		TPS72xx³
	VI	5		2	PG
		IN	PG
		6		1	250 kΩ
		IN	SENSE
			OUT	7	VO
	0.1 μF	4		8
			OUT
		EN			CO
			GND		(see Note A)
					+
			3		10 μF
					CSR = 1 Ω

³ TPS7225Q, TPS7228Q² , TPS7230Q, TPS7233Q, TPS7248Q, TPS7250Q

(fixed-voltage options)

NOTE A: Capacitor selection is nontrivial. See application information section for details.

Figure 2. Typical Application Configuration

² This device is in the product preview stage of development. Please contact the local TI sales office for availability.

2	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q

TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY

MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998

TPS72xx chip information

These chips, when properly assembled, display characteristics similar to the TPS72xxQ. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

7	6	4
		5

57

1

2	3
	69

					(5)
			(3)		SENSE
	IN				(6)
					FB
				TPS72xx
			(2)		(4)
	EN				OUT
					(7)
					PG

(1)

GND

CHIP THICKNESS: 15 MILS TYPICAL

BONDING PADS: 4 × 4 MILS MINIMUM

TJmax = 150°C

TOLERANCES ARE ± 10%.

ALL DIMENSIONS ARE IN MILS.

²Fixed-voltage options only (TPS7225, TPS7228#,

TPS7230, TPS7233, TPS7248, and TPS7250)

³Adjustable version only (TPS7201)

NOTE A. For most applications, OUT and SENSE should be tied together as close as possible to the device; for other implementations, refer to the SENSE-pin connection discussion in the application information section of this data sheet.

functional block diagram

IN
EN	§	§	§
	_
	+

	1.12 V
	+
	_
Vref = 1.188 V	R1
	R2

PG

OUT

SENSE¶ /FB

RESISTOR DIVIDER OPTIONS

DEVICE	R1	R2	UNIT
TPS7201	0	∞	W
TPS7225	257	233	kW
TPS7228#	306	233	kW
TPS7230	357	233	kW
TPS7233	420	233	kW
TPS7248	726	233	kW
TPS7250	756	233	kW

NOTE A: Resistors are nominal values only.

COMPONENT COUNT

MOS transistors	108
Bilpolar transistors	41
Diodes	4
Capacitors	15
Resistors	75

GND

§ Switch positions are shown with EN low (active).

¶For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to the SENSE-pin connection discussion in application information section.

#This device is in the product preview stage of development. Please contact the local TI sales office for availability.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

3

TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q

TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY

MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Input voltage range , VI, PG, SENSE, EN . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . ±0.3 V to 11	V
Output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5	A
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . ±55°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .	. . . . . . . . . . . . . . . . . . . ±65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . .	. . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

²Stresses beyond those listed under ªabsolute maximum ratingsº may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ªrecommended operating conditionsº is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

³ All voltage values are with respect to network ground terminal.

DISSIPATION RATING TABLE 1 ± FREE-AIR TEMPERATURE (see Note 1 and Figure 3)

	PACKAGE	TA ≤ 25°C	DERATING FACTOR	TA = 70°C	TA = 85°C	TA = 125°C
		POWER RATING	ABOVE TA = 25°C	POWER RATING	POWER RATING	POWER RATING
	D	725 mW	5.8 mW/°C	464 mW	377 mW	145 mW
	P	1175 mW	8.74 mW/°C	782 mW	650 mW	301 mW
	PW	525 mW	4.2 mW/°C	336 mW	273 mW	105 mW
		DISSIPATION RATING TABLE 2 ± CASE TEMPERATURE (see Note 1 and Figure 4)
	PACKAGE	TC ≤ 25°C	DERATING FACTOR	TC = 70°C	TC = 85°C	TC = 125°C
		POWER RATING	ABOVE TC = 25°C	POWER RATING	POWER RATING	POWER RATING
	D	2063 mW	16.5 mW/°C	1320 mW	1073 mW	413 mW
	P	2738 mW	20.49 mW/°C	1816 mW	1508 mW	689 mW
	PW	2900 mW	23.2 mW/°C	1856 mW	1508 mW	580 mW

NOTE 1: Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute maximum of 150°C. For guidelines on maintaining junction temperature within the recommended operating range, see application information section.

		MAXIMUM CONTINUOUS DISSIPATION
			vs
		FREE-AIR TEMPERATURE
mW±	1200
	1100
Dissipation	1000		P Package
			RθJA = 114.4°C/W
	900
	800
Continuous	700			D Package
				RθJA = 172°C/W
	600
	500
Maximum±	400
	300	RθJA = 238°C/W
	200	PW Package
D	100
P
	0
	25	50	75	100	125	150
		TA ± Free-Air Temperature ± °C

Figure 3

MAXIMUM CONTINUOUS DISSIPATION

			vs
			CASE TEMPERATURE
mW	3000		P Package
			RθJC = 48.8°C/W
±
Dissipation	2500
	2000		PW Package
Continuous			RθJC = 43.1°C/W
	1500
	1000
Maximum
			D Package
		RθJC = 60.6°C/W
	500
±
D
P
	0
	25	50	75	100	125	150
			TC ± Case Temperature ± °C

Figure 4

4	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q

TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY

MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998

recommended operating conditions

						MIN	MAX	UNIT
					TPS7201Q	3	10
					TPS7225Q	3.65	10
					TPS7228Q³	TBD	10
Input voltage, VI²					TPS7230Q	3.96	10	V
					TPS7233Q	3.98	10
					TPS7248Q	5.24	10
					TPS7250Q	5.41	10
High-level input voltage at				VIH		2		V
		EN,
Low-level input voltage at			VIL				0.5	V
	EN,
Output current, IO						0	250	mA
Operating virtual junction temperature, TJ						± 40	125	°C

²Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:

VI(min) + VO(max) )VDO(max load)

Because the TPS7201 is programmable, rDS(on) should be used to calculate VDO before applying the above equation. The equation for

calculating VDO from rDS(on) is given in Note 3 under the TPS7201 electrical characteristics table. The minimum value of 3 V is the absolute lower limit for the recommended input-voltage range for the TPS7201.

³ This device is in the product preview stage of development. Please contact the local TI sales office for availability.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

5

TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q

TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY

MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998

electrical characteristics, IO = 10 mA, EN = 0 V, CO = 4.7 μF (CSR² = 1 Ω), SENSE/FB shorted to OUT

(unless otherwise noted)

		PARAMETER			TEST CONDITIONS³			T	TPS72xxQ		UNIT
								J	MIN TYP	MAX
								25°C	180	225
	Ground current (active mode)		EN ≤ 0.5 V,			VI = VO + 1 V,					μA
			0 mA ≤ IO ≤ 250 mA				± 40°C to 125°C			325
	Input current (standby mode)				= VI,	3 V ≤ VI ≤ 10 V		25°C		0.5	μA
				EN
							± 40°C to 125°C			1
	Output current limit threshold		VO = 0 V			VI = 10 V		25°C	0.6	1	A
							± 40°C to 125°C			1.5
	Pass-element leakage current in							25°C		0.5	μA
			EN = VI,			3 V ≤ VI ≤ 10 V
	standby mode						°	°		1
							± 40 C to 125 C
	PG leakage current		VPG = 10 V,			Normal operation		25°C		0.5	μA
							± 40°C to 125°C			0.5
	Output voltage temperature coefficient						± 40°C to 125°C		31	75	ppm/°C
	Thermal shutdown junction temperature								165		°C
			3 V ≤ VI ≤ 6 V				±40°C to 125°C		2		V
	EN logic high (standby mode)
			6 V ≤ VI ≤ 10 V						2.7
		logic low (active mode)	3 V ≤ VI ≤ 10 V					25°C		0.5	V
	EN
							± 40°C to 125°C			0.5
		hysteresis voltage						25°C	50		mV
	EN
		input current	0 V ≤ VI ≤ 10 V					25°C	± 0.5	0.5	μA
	EN
							± 40°C to 125°C		± 0.5	0.5
	Minimum VI for active pass element							25°C	1.9	2.5	V
							± 40°C to 125°C			2.5
	Minimum VI for valid PG		IPG = 300 μA					25°C	1.1	1.5	V
							± 40°C to 125°C			1.9

²CSR(compensation series resistance) refers to the total series resistance, including the equivalent series resistance (ESR) of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

6	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q

TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY

MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998

TPS7201Q electrical characteristics, IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 μF (CSR² = 1 Ω), FB shorted to OUT at device leads (unless otherwise noted)

PARAMETER

TEST CONDITIONS³

T

TPS7201Q

UNIT

J

MIN

TYP

MAX

Reference voltage (measured

VI = 3.5 V,

IO = 10 mA

25°C

1.188

V

at FB with OUT connected to

3 V ≤ VI ≤ 10 V,

5 mA ≤ IO ≤ 250 mA,

± 40°C to 125°C

1.152

1.224

V

FB)

See Note 2

Reference voltage

± 40°C to 125°C

31

75

ppm/°C

temperature coefficient

VI = 2.4 V,§

50 mA ≤ IO ≤ 100 mA

25°C

2.1

VI = 2.4 V,§

100 mA ≤ IO ≤ 200 mA

25°C

2.9

Pass-element series

VI = 2.9 V,

50 mA ≤ IO ≤ 250 mA

25°C

1.6

2.7

Ω

resistance (see Note 3)

± 40°C to 125°C

4.5

VI = 3.9 V,

50 mA ≤ IO ≤ 250 mA

25°C

1

VI = 5.9 V,

50 mA ≤ IO ≤ 250 mA

25°C

0.8

μ

25°C

23

Input regulation

VI = 3 V to 10 V,

50 A ≤ IO ≤ 250 mA,

mV

See Note 2

± 40°C to 125°C

36

IO = 5 mA to 250 mA,

3 V ≤ VI ≤ 10 V,

25°C

15

25

Output regulation

See Note 2

± 40°C to 125°C

36

mV

IO = 50 mA to 250 mA,

3 V ≤ VI ≤ 10 V,

25°C

17

27

See Note 2

± 40°C to 125°C

43

IO = 50 mA

25°C

49

60

Ripple rejection

f = 120 Hz

± 40°C to 125°C

32

dB

IO = 250 mA,

25°C

45

50

See Note 2

± 40°C to 125°C

30

25°C

Output noise spectral density

f = 120 Hz

2

mV/√

Hz

10 Hz ≤ f ≤ 100 kHz,

CO = 4.7 mF

25°C

235

Output noise voltage

CO = 10 mF

25°C

190

mVrms

CSR² = 1 Ω

CO = 100 mF

25°C

125

PG trip-threshold voltage¶

V

FB

voltage decreasing from above V

± 40°C to 125°C

0.95 ×

V

VFB(nom)

PG

PG hysteresis voltage¶

Measured at VFB

25°C

12

mV

PG output low voltage¶

I

= 400 mA,

V

I

= 2.13 V

25°C

0.1

0.4

V

PG

± 40°C to 125°C

0.4

FB input current

25°C

± 10

0.1

10

nA

± 40°C to 125°C

± 20

20

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

§ This voltage is not recommended.

¶ Output voltage programmed to 2.5 V with closed-loop configuration (see application information).

NOTES: 2. When VI < 2.9 V and IO > 100 mA simultaneously, pass element rDS(on) increases (see Figure 10) to a point such that the resulting dropout voltage prevents the regulator from maintaining the specified tolerance range.

3. To calculate dropout voltage, use equation:

VDO = IO rDS(on)

rDS(on) is a function of both output current and input voltage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and 5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other

programmed values, refer to Figures 10 and 11.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

7

TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q

TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY

MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998

TPS7225Q electrical characteristics, IO = 10 mA, VI = 3.5 V, EN = 0 V, CO = 4.7 μF (CSR² = 1 Ω), SENSE shorted to OUT (unless otherwise noted)

PARAMETER	TEST CONDITIONS³		T		TPS7225Q		UNIT
			J	MIN	TYP	MAX
Output voltage	VI = 3.5 V,	IO = 10 mA	25°C		2.5		V
	3.5 V ≤ VI ≤ 10 V,	5 mA ≤ IO ≤ 250 mA	± 40°C to 125°C	2.45		2.55
Dropout voltage	IO = 250 mA,	VI = 2.97 V	25°C		560	850	mV
			± 40°C to 125°C			1.1	V
Pass-element series resistance	(2.97 V ± VO)/IO,	VI = 2.97 V,	25°C		2.24	3.4	Ω
	IO = 250 mA		± 40°C to 125°C			3.84
Input regulation	VI = 3.5 V to 10 V,	50 mA ≤ IO ≤ 250 mA	25°C		9	27	mV
			± 40°C to 125°C			33
	IO = 5 mA to 250 mA,	3.5 V ≤ VI ≤ 10 V	25°C		28	36
Output regulation			± 40°C to 125°C			60	mV
	IO = 50 mA to 250 mA,	3.5 V ≤ VI ≤ 10 V	25°C		24	41
			± 40°C to 125°C			73
		IO = 50 mA	25°C	47	58
Ripple rejection	f = 120 Hz		± 40°C to 125°C	45			dB
		IO = 250 mA	25°C	40	46
			± 40°C to 125°C	38
			25°C
Output noise spectral density	f = 120 Hz				2		mV/√	Hz
	10 Hz ≤ f ≤ 100 kHz,	CO = 4.7 mF	25°C		248
Output noise voltage		CO = 10 mF	25°C		200		mVrms
	CSR² = 1 Ω
		CO = 100 mF	25°C		130
PG trip-threshold voltage	VO voltage decreasing from above VPG		± 40°C to 125°C		0.95 ×		V
					VO(nom)
PG hysteresis voltage			25°C		50		mV
PG output low voltage	IPG = 1.2 mA,	VI = 2.13 V	25°C		0.3	0.44	V
			± 40°C to 125°C			0.5

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

8	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

				TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q
				TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY
	MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
					SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998
TPS7228Q electrical characteristics, I		O	= 10 mA, V = 3.75 V, EN = 0 V, C				O	= 4.7 μF (CSR² = 1 Ω),
				I
SENSE shorted to OUT (unless otherwise noted)
PARAMETER	TEST CONDITIONS³					T			TPS7228Q	UNIT
						J	MIN		TYP	MAX
Output voltage	VI = 3.75 V,			IO = 10 mA		25°C			2.75	V
	3.75 V ≤ VI ≤ 10 V,			5 mA ≤ IO ≤ 250 mA	± 40°C to 125°C
							2.69			2.81
	IO = 10 mA,			VI = 2.69 V		25°C			TBD
					± 40°C to 125°C					TBD
Dropout voltage	IO = 100 mA,			VI = 2.69 V		25°C			TBD	mV
					± 40°C to 125°C
										TBD
	IO = 250 mA,			VI = 2.69 V		25°C			TBD
					± 40°C to 125°C					TBD
Pass-element series resistance	(2.69 V ± VO)/IO,			VI = 2.69 V,		25°C			TBD
										Ω
	I = 250 mA				°	°
										TBD
	O				± 40 C to 125 C
Input regulation	VI = 3.75 V to 10 V,			50 μA ≤ IO ≤ 250 mA		25°C			TBD	mV
					± 40°C to 125°C
										TBD
	IO = 5 mA to 250 mA,			3.75 V ≤ VI ≤ 10 V		25°C			TBD
					± 40°C to 125°C					TBD
Output regulation
						25°C			TBD	mV
	IO = 50 μA to 250 mA,			3.75 V ≤ VI ≤ 10 V
					± 40°C to 125°C					TBD
				IO = 50 μA		25°C			TBD
					± 40°C to 125°C				TBD
Ripple rejection	f = 120 Hz									dB
						25°C			TBD
				IO = 250 mA
					± 40°C to 125°C				TBD
Output noise spectral density	f = 120 Hz					25°C			TBD	μV/√ Hz
	10 Hz ≤ f ≤ 100 kHz,			CO = 4.7 μF		25°C			TBD
Output noise voltage				CO = 10 μF		25°C			TBD	μVrms
	CSR² = 1 Ω
				CO = 100 μF		25°C			TBD
PG trip-threshold voltage	VO voltage decreasing from above VPG				± 40°C to 125°C				TBD	V
PG hysteresis voltage						25°C			TBD	mV
PG output low voltage	IPG = 1.2 mA,			VI = 2.34 V		25°C				TBD
					± 40°C to 125°C					V
										TBD

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

9

TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q

TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY

MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998

TPS7230Q electrical characteristics, IO = 10 mA, VI = 4 V, EN = 0 V, CO = 4.7 μF (CSR² = 1 Ω), SENSE shorted to OUT (unless otherwise noted)

PARAMETER	TEST CONDITIONS³		T		TPS7230Q		UNIT
			J	MIN	TYP	MAX
Output voltage	VI = 4 V,	IO = 10 mA	25°C		3		V
	4 V ≤ VI ≤ 10 V,	5 mA ≤ IO ≤ 250 mA	± 40°C to 125°C	2.94		3.06
	IO = 100 mA,	VI = 2.97 V	25°C		145	185
Dropout voltage			± 40°C to 125°C			270	mV
	IO = 250 mA,	VI = 2.97 V	25°C		390	502
			± 40°C to 125°C			900
Pass-element series resistance	(2.97 V ± VO)/IO,	VI = 2.97 V,	25°C		1.56	2.01	Ω
	IO = 250 mA		± 40°C to 125°C			3.6
Input regulation	VI = 4 V to 10 V,	50 mA ≤ IO ≤ 250 mA	25°C		9	27	mV
			± 40°C to 125°C			33
	IO = 5 mA to 250 mA,	4 V ≤ VI ≤ 10 V	25°C		34	45
Output regulation			± 40°C to 125°C			74	mV
	IO = 50 mA to 250 mA,	4 V ≤ VI ≤ 10 V	25°C		42	60
			± 40°C to 125°C			98
		IO = 50 mA	25°C	45	56
Ripple rejection	f = 120 Hz		± 40°C to 125°C	44			dB
		IO = 250 mA	25°C	40	45
			± 40°C to 125°C	38
Output noise spectral density	f = 120 Hz		25°C		2		mV/√	Hz
	10 Hz ≤ f ≤ 100 kHz,	CO = 4.7 mF	25°C		256
Output noise voltage		CO = 10 mF	25°C		206		mVrms
	CSR² = 1 Ω
		CO = 100 mF	25°C		132
PG trip-threshold voltage	VO voltage decreasing from above VPG		± 40°C to 125°C		0.95 ×		V
					VO(nom)
PG hysteresis voltage			25°C		50		mV
PG output low voltage	IPG = 1.2 mA,	VI = 2.55 V	25°C		0.25	0.44	V
			± 40°C to 125°C			0.44

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

10	POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

TPS7201Q, TPS7225Q, TPS7228Q, TPS7230Q

TPS7233Q, TPS7248Q, TPS7250Q, TPS72xxY

MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS

SLVS102F ± MARCH 1995 ± REVISED NOVEMBER 1998

TPS7233Q electrical characteristics, IO = 10 mA, VI = 4.3 V, EN = 0 V, CO = 4.7 μF (CSR² = 1 Ω), SENSE shorted to OUT (unless otherwise noted)

PARAMETER	TEST CONDITIONS³		T		TPS7233Q		UNIT
			J	MIN	TYP	MAX
Output voltage	VI = 4.3 V,	IO = 10 mA	25°C		3.3		V
	4.3 V ≤ VI ≤ 10 V,	5 mA ≤ IO ≤ 250 mA	± 40°C to 125°C	3.23		3.37
	IO = 10 mA,	VI = 3.23 V	25°C		14	20
			± 40°C to 125°C			30
Dropout voltage	IO = 100 mA,	VI = 3.23 V	25°C		140	180	mV
			± 40°C to 125°C			232
	IO = 250 mA,	VI = 3.23 V	25°C		360	460
			± 40°C to 125°C			610
Pass-element series resistance	(3.23 V ± VO)/IO,	VI = 3.23 V,	25°C		1.5	1.84	Ω
	IO = 250 mA		± 40°C to 125°C			2.5
Input regulation	VI = 4.3 V to 10 V,	50 mA ≤ IO ≤ 250 mA	25°C		8	25	mV
			± 40°C to 125°C			33
	IO = 5 mA to 250 mA,	4.3 V ≤ VI ≤ 10 V	25°C		32	42
Output regulation			± 40°C to 125°C			71	mV
	IO = 50 mA to 250 mA,	4.3 V ≤ VI ≤ 10 V	25°C		41	55
			± 40°C to 125°C			98
		IO = 50 mA	25°C	40	52
Ripple rejection	f = 120 Hz		± 40°C to 125°C	38			dB
		IO = 250 mA	25°C	35	44
			± 40°C to 125°C	33
			25°C
Output noise spectral density	f = 120 Hz				2		mV/√	Hz
	10 Hz ≤ f ≤ 100 kHz,	CO = 4.7 mF	25°C		265
Output noise voltage		CO = 10 mF	25°C		212		mVrms
	CSR² = 1 Ω
		CO = 100 mF	25°C		135
PG trip-threshold voltage	VO voltage decreasing from above VPG		± 40°C to 125°C		0.95 ×		V
					VO(nom)
PG hysteresis voltage			25°C		32		mV
PG output low voltage	IPG = 1.2 mA,	VI = 2.8 V	25°C		0.22	0.4	V
			± 40°C to 125°C			0.4

²CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance to CO.

³Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be taken into account separately.

POST OFFICE BOX 655303 •DALLAS, TEXAS 75265

11